ARM Cortex A9 User Manual

Functional Description
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Reset modes
The reset signals present in the Cortex-A9 design enable you to reset different parts of the
processor independently. Table 2-1 shows the reset signals, and the combinations and possible
applications that you can use them in.
Power-on reset
You must apply power-on or cold reset to the Cortex-A9 uniprocessor when power is first
applied to the system. In the case of power-on reset, the leading edge, that is the falling edge, of
the reset signals do not have to be synchronous to CLK, but the rising edge must be.
You must assert the reset signals for at least nine CLK cycles to ensure correct reset behavior.
ARM recommends the following reset sequence:
1. Apply nCPURESET and nDBGRESET, plus nNEONRESET if the SIMD MPE is
present.
2. Wait for at least nine CLK cycles, plus at least one cycle in each other clock domain, or
more if the documentation for other components requires it. There is no harm in applying
more clock cycles than this, and maximum redundancy can be achieved by applying 15
cycles on every clock domain.
3. Stop the CLK clock input to the Cortex-A9 uniprocessor. If there is a data engine present,
use NEONCLKOFF. See Configuration signals on page A-5.
4. Wait for the equivalent of approximately 10 cycles, depending on your implementation.
This compensates for clock and reset tree latencies.
5. Release all resets.
6. Wait for the equivalent of another approximately 10 cycles, again to compensate for clock
and reset tree latencies.
7. Restart the clock.
Software reset
A processor or warm reset initializes the majority of the Cortex-A9 processor, apart from its
debug logic. Breakpoints and watchpoints are retained during a processor reset. Processor reset
is typically used for resetting a system that has been operating for some time. Use the same reset
sequence described in Power-on reset with the only difference that nDBGRESET must remain
HIGH during the sequence, to ensure that all values in the debug registers are maintained.
Table 2-1 Reset modes
Mode nCPURESET nNEONRESET nDBGRESET
Power-on reset, cold reset 0 0 0
Processor reset, soft or warm reset 0 0 1
SIMD MPE power-on reset 1 0 1
Debug logic reset 1 1 0
No reset, normal run mode 1 1 1

ARM Cortex A9 Specifications

General

Architecture	ARMv7-A
Cores	1-4
SIMD Extensions	NEON
ISA	ARM
Microarchitecture	Cortex-A9
Instruction Width	32-bit
Data Width	32-bit
MMU	Yes
Instruction Set	ARMv7-A
Clock Speed	Up to 2 GHz
L1 Cache	32 KB Instruction, 32 KB Data (per core)
Process Technology	40 nm, 28 nm
Floating Point Unit	VFPv3
Pipeline Depth	8 stages
Power Consumption	Low power design