ARM Cortex A9 User Manual

ARM DDI 0388I Copyright © 2008-2012 ARM. All rights reserved. C-1
ID073015 Non-Confidential
Appendix C
Revisions
This appendix describes the technical changes between released issues of this book.
Table C-1 Issue A
Change Location
First release -
Table C-2 Differences between issue A and issue B
Change Location
Clarified Load/Store Unit and address generation. Figure 1-1 on page 1-2.
Changed fast loop mode to small loop mode. • Figure 1-1 on page 1-2
• Small loop mode on page 1-3
• Instruction cache features on page 7-2
• About power consumption control on page 12-6.
Changed branch prediction to dynamic branch prediction. • Features on page 1-6
• About the L1 instruction side memory system on page 7-5
• Branch instructions on page B-8.
Changed LI cache coherency to L1 data cache coherency. Cortex-A9 variants on page 1-4.
Corrected Processor Feature Register 0 reset value. Table 4-29 on page 4-46.

ARM Cortex A9 Specifications

General

Architecture	ARMv7-A
Cores	1-4
SIMD Extensions	NEON
ISA	ARM
Microarchitecture	Cortex-A9
Instruction Width	32-bit
Data Width	32-bit
MMU	Yes
Instruction Set	ARMv7-A
Clock Speed	Up to 2 GHz
L1 Cache	32 KB Instruction, 32 KB Data (per core)
Process Technology	40 nm, 28 nm
Floating Point Unit	VFPv3
Pipeline Depth	8 stages
Power Consumption	Low power design