ARM DDI 0388I Copyright © 2008-2012 ARM. All rights reserved. C-1
ID073015 Non-Confidential
Appendix C
Revisions
This appendix describes the technical changes between released issues of this book.
Table C-1 Issue A
Change Location
First release -
Table C-2 Differences between issue A and issue B
Change Location
Clarified Load/Store Unit and address generation. Figure 1-1 on page 1-2.
Changed fast loop mode to small loop mode. • Figure 1-1 on page 1-2
• Small loop mode on page 1-3
• Instruction cache features on page 7-2
• About power consumption control on page 12-6.
Changed branch prediction to dynamic branch prediction. • Features on page 1-6
• About the L1 instruction side memory system on page 7-5
• Branch instructions on page B-8.
Changed LI cache coherency to L1 data cache coherency. Cortex-A9 variants on page 1-4.
Corrected Processor Feature Register 0 reset value. Table 4-29 on page 4-46.
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