ARM Cortex A9 User Manual

Introduction
ARM DDI 0388I Copyright © 2008-2012 ARM. All rights reserved. 1-12
ID073015 Non-Confidential
1.9 Product revisions
This section describes the differences in functionality between product revisions:
r0p0 First release.
r0p0-r0p1 The only differences between the two revisions are:
• r0p1 includes fixes for all known engineering errata relating to r0p0
• r0p1 includes an upgrade of the micro TLB entries from 8 to 32 entries, on
both the Instruction and Data side.
Neither of these changes affect the functionality described in this document.
r0p1-r1p0 Functional changes are:
• r1p0 includes fixes for all known engineering errata relating to r0p1.
• In r1p0 CPUCLKOFF and DECLKOFF enable control of Cortex-A9
processors during reset sequences. See Configuration signals on page A-5.
— In a multiprocessor implementation of the design there are as many
CPUCLKOFF pins as there are Cortex-A9 processors.
— DECLKOFF controls the data engine clock during reset sequences.
• r1p0 includes dynamic high level clock gating of the Cortex-A9 processor.
See Dynamic high level clock gating on page 2-8.
— MAXCLKLATENCY[2:0] bus added. See Configuration signals
on page A-5
— Addition of CP15 power control register. See Power Control Register
on page 4-41.
• Extension of the Performance Monitoring Event bus. In r1p0,
PMUEVENT is 52 bits wide:
— Addition of Cortex-A9 specific events. See Table 2-2 on page 2-5.
— Event descriptions extended. See Table 2-2 on page 2-5.
• Addition of PMUSECURE and PMUPRIV. See Performance monitoring
signals on page A-14.
• Main TLB options for 128 entries or 64 entries. See TLB Type Register on
page 4-19.
• DEFLAGS[6:0] added. See DEFLAGS[6:0] on page 4-37.
• The power management signal BISTSCLAMP is removed.
• The scan test signal SCANTEST is removed.
• Addition of a second replacement strategy. Selection done by SCTLR.RR
bit. See System Control Register on page 4-25.
• Addition of PL310 cache controller optimization description. See
Optimized accesses to the L2 memory interface on page 8-7.
• Change to the serializing behavior of
DMB . See Serializing instructions on
page B-9.
• ID Register values changed to reflect correct revision.

ARM Cortex A9 Specifications

General

Architecture	ARMv7-A
Cores	1-4
SIMD Extensions	NEON
ISA	ARM
Microarchitecture	Cortex-A9
Instruction Width	32-bit
Data Width	32-bit
MMU	Yes
Instruction Set	ARMv7-A
Clock Speed	Up to 2 GHz
L1 Cache	32 KB Instruction, 32 KB Data (per core)
Process Technology	40 nm, 28 nm
Floating Point Unit	VFPv3
Pipeline Depth	8 stages
Power Consumption	Low power design