ARM Cortex A9 User Manual

Introduction
ARM DDI 0388I Copyright © 2008-2012 ARM. All rights reserved. 1-13
ID073015 Non-Confidential
r1p0-r2p0 Functional changes are:
• Addition of optional Preload Engine hardware feature and support.
— PLE bit added to NSACR. See Non-secure Access Control Register
on page 4-32.
— Preload Engine registers added. See c11 registers on page 4-10.
— Preload operations added and MCRR instruction added. See
Chapter 9 Preload Engine.
— Addition of Preload Engine events.
See Performance monitoring on page 2-3, Table 11-6 on page 11-8,
and Table A-18 on page A-14.
• Change to voltage domains. See Figure 2-4 on page 2-14.
• NEON Busy Register. See NEON Busy Register on page 4-42.
• ID Register values changed to reflect correct revision.
r2p0-r2p1 No functional changes.
r2p1-r2p2 No functional changes. Documentation updates and corrections only. See
Differences between issue D and issue F on page C-6.
r2p2-r3p0 Addition of the REVIDR. See Revision ID register on page 4-21.
r3p0-r4p0 Functional changes are:
• Addition of new hardware configuration options for the TLB, BTAC, GHB
and Instruction micro TLB sizes. See Configurable options on page 1-8.
• Enhanced data prefetching mechanism. See Data prefetching on page 7-11
r4p0-r4p1 No change.

ARM Cortex A9 Specifications

General

Architecture	ARMv7-A
Cores	1-4
SIMD Extensions	NEON
ISA	ARM
Microarchitecture	Cortex-A9
Instruction Width	32-bit
Data Width	32-bit
MMU	Yes
Instruction Set	ARMv7-A
Clock Speed	Up to 2 GHz
L1 Cache	32 KB Instruction, 32 KB Data (per core)
Process Technology	40 nm, 28 nm
Floating Point Unit	VFPv3
Pipeline Depth	8 stages
Power Consumption	Low power design