ARM Cortex A9 User Manual

System Control
ARM DDI 0388I Copyright © 2008-2012 ARM. All rights reserved. 4-42
ID073015 Non-Confidential
4.3.23 NEON Busy Register
The NEON Busy Register characteristics are:
Purpose Enables software to determine if a NEON instruction is executing.
Usage constraints • a read-only register in Secure state
• a read-only register in Non-secure state.
Configurations Available in all configurations.
Attributes See the register summary in Table 4-15 on page 4-11.
Figure 4-22 shows the NEON Busy Register bit assignments
Figure 4-22 NEON Busy Register bit assignments
Table 4-49 shows the NEON Busy Register bit assignments.
To access the NEON Busy Register, read the CP15 register with:
MRC p15,0,<Rd>,c15,c1,0; Read NEON Busy Register
4.3.24 Configuration Base Address Register
The Configuration Base Address Register characteristics are:
Purpose Takes the physical base address value at reset.
Usage constraints The Configuration Base Address Register is:
• read/write in secure privileged modes
• read-only in non-secure state
• read-only in User mode.
Configurations In Cortex-A9 uniprocessor implementations the base address is set to zero.
In Cortex-A9 MPCore implementations, the base address is reset to
PERIPHBASE[31:13] so that software can determine the location of the
private memory region.
Attributes See the register summary in Table 4-15 on page 4-11.
Figure 4-23 on page 4-43 shows the Configuration Base Address Register bit assignments.
31 1
NEON busy
0
Reserved
Table 4-49 NEON Busy Register bit assignments
Bits Name Function
[31:1] - Reserved.
[0] NEON busy Software can use this to determine if a NEON instruction is executing. This bit is set to 1 if there is a NEON
instruction in the NEON pipeline, or in the processor pipeline.

ARM Cortex A9 Specifications

General

Architecture	ARMv7-A
Cores	1-4
SIMD Extensions	NEON
ISA	ARM
Microarchitecture	Cortex-A9
Instruction Width	32-bit
Data Width	32-bit
MMU	Yes
Instruction Set	ARMv7-A
Clock Speed	Up to 2 GHz
L1 Cache	32 KB Instruction, 32 KB Data (per core)
Process Technology	40 nm, 28 nm
Floating Point Unit	VFPv3
Pipeline Depth	8 stages
Power Consumption	Low power design