System Control
ARM DDI 0388I Copyright © 2008-2012 ARM. All rights reserved. 4-11
ID073015 Non-Confidential
4.2.14 c13 registers
Table 4-14 shows the CP15 system control registers you can access when CRn is c13.
4.2.15 c14 registers
No CP15 system control registers are accessed with CRn set to c14.
4.2.16 c15 registers
Table 4-15 shows the CP15 system control registers you can access when CRn is c15.
Table 4-14 c13 register summary
Op1 CRm Op2 Name Type Reset Description
0c00FCSEIDR RW
0x00000000
Deprecated registers on page 4-2
1 CONTEXTIDR RW - Context ID Register
2 TPIDRURW
RW
a
a. RW in User mode.
- Software Thread ID registers
3 TPIDRURO
RO
b
b. RO in User mode.
-
4 TPIDRPRW. RW -
Table 4-15 c15 system control register summary
Op1 CRm Op2 Name Type Reset Description
0 c0 0 Power Control Register
RW
a
-
b
Power Control Register on page 4-41
c1 0 NEON Busy Register RO
0x00000000
NEON Busy Register on page 4-42
4 c0 0 Configuration Base Address
RO
c
-
d
Configuration Base Address Register on page 4-42
5 c4 2 Select Lockdown TLB Entry
for read
WO
e
- TLB lockdown operations on page 4-43
4 Select Lockdown TLB Entry
for write
WO
e
-
c5 2 Main TLB VA register
RW
e
-
c6 2 Main TLB PA register
RW
e
-
c7 2 Main TLB Attribute register
RW
e
-
a. RW in Secure state. RO in Non-secure state.
b. Reset value depends on the MAXCLKLATENCY[2:0] value. See Configuration signals on page A-5.
c. RW in secure privileged mode and RO in Non-secure state and User secure state.
d. In Cortex-A9 uniprocessor implementations the configuration base address is set to zero.
In Cortex-A9 MPCore implementations the configuration base address is reset to PERIPHBASE[31:13] so that software can determine
the location of the private memory region.
e. No access in Non-secure state.
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