ARM Cortex A9 User Manual

System Control
ARM DDI 0388I Copyright © 2008-2012 ARM. All rights reserved. 4-12
ID073015 Non-Confidential
4.2.17 Identification Registers
The Processor ID Registers are Read-Only registers that return the values stored in the Main ID
and feature registers of the processor. You must use the CP15 interface to access these registers.
Table 4-16 shows the name, type, value and description that is associated with each Processor
ID Register.
See the ARM Architecture Reference Manual for more information on the Processor ID
Registers.
Table 4-16 Processor ID Registers
CRn Op1 CRM Op2 Name Type Value Description
c0 0 c0 0 MIDR RO Product
revision
dependant
Main ID Register on page 4-18
1CTR RO
0x83338003 Cache Type Register
2TCMTR RO
0x00000000 TCM Type Register
3
TLBTR
a
RO - TLB Type Register on page 4-19
5MPIDR RO- Multiprocessor Affinity Register on page 4-19
6REVIDRRO- Revision ID register on page 4-21
c1 0 ID_PFR0 RO
0x00001231 Processor Feature Register 0
1ID_PFR1RO
0x00000011 Processor Feature Register 1
2 ID_DFR0 RO
0x00010444 Debug Feature Register 0
3 ID_AFR0 RO
0x00000000 Auxiliary Feature Register 0
4ID_MMFR0RO
0x00100103 Memory Model Feature Register 0
5ID_MMFR1RO
0x20000000 Memory Model Feature Register 1
6ID_MMFR2RO
0x01230000 Memory Model Feature Register 2
7ID_MMFR3RO
0x00102111 Memory Model Feature Register 3
c2 0 ID_ISAR0 RO
0x00101111 Instruction Set Attribute Register 0
1ID_ISAR1RO
0x13112111 Instruction Set Attribute Register 1
2ID_ISAR2RO
0x21232041 Instruction Set Attribute Register 2
3ID_ISAR3RO
0x11112131 Instruction Set Attribute Register 3
4ID_ISAR4RO
0x00011142 Instruction Set Attribute Register 4
1 c0 0 CCSIDR RO - Cache Size Identification Register on page 4-21
1CLIDR RO
0x09000003 Cache Level ID Register on page 4-22
7AIDR RO
0x00000000 Auxiliary ID Register on page 4-23
2c00CSSELRRW- Cache Size Selection Register on page 4-24
a. Depends on TLBSIZE. See TLB Type Register on page 4-19.

ARM Cortex A9 Specifications

General

Architecture	ARMv7-A
Cores	1-4
SIMD Extensions	NEON
ISA	ARM
Microarchitecture	Cortex-A9
Instruction Width	32-bit
Data Width	32-bit
MMU	Yes
Instruction Set	ARMv7-A
Clock Speed	Up to 2 GHz
L1 Cache	32 KB Instruction, 32 KB Data (per core)
Process Technology	40 nm, 28 nm
Floating Point Unit	VFPv3
Pipeline Depth	8 stages
Power Consumption	Low power design