ARM Cortex A9 User Manual

System Control
ARM DDI 0388I Copyright © 2008-2012 ARM. All rights reserved. 4-19
ID073015 Non-Confidential
4.3.2 TLB Type Register
The TLBTR characteristics are:
Purpose Returns the number of lockable entries for the TLB.
Usage constraints The TLBTR is:
• common to the Secure and Non-secure states
• only accessible in privileged mode.
Configurations Available in all configurations.
Attributes See the register summary in Table 4-2 on page 4-5.
Figure 4-2 shows the TLBTR bit assignments.
Figure 4-2 TLBTR bit assignments
Table 4-29 shows the TLBTR bit assignments.
To access the TLBTR, read the CP15 register with:
MRC p15,0,<Rd>,c0,c0,3; returns TLB details
4.3.3 Multiprocessor Affinity Register
The MPIDR characteristics are:
Purpose To identify:
• whether the processor is part of a Cortex-A9 MPCore
implementation
31 24 23 16 15 8 7 3 2 1
0
SBZ/UNPDLSizeILSizeSBZ
TLB_size
nU
Table 4-29 TLBTR bit assignments
Bits Name Function
[31:24] SBZ -
[23:16] ILsize Specifies the number of instruction TLB lockable entries.
For the Cortex-A9 processor, this is 0.
[15:8] DLsize Specifies the number of unified or data TLB lockable entries.
For the Cortex-A9 processor, this is 4.
[7:3] SBZ or UNP -
[2:1] TLB_size 00 TLB has 64 entries
01 TLB has 128 entries
10 TLB has 256 entries
11 TLB has 512 entries.
[0] nU Specifies if the TLB is unified, 0, or if there are separate instruction and data TLBs.
0 The Cortex-A9 processor has a unified TLB.

ARM Cortex A9 Specifications

General

Architecture	ARMv7-A
Cores	1-4
SIMD Extensions	NEON
ISA	ARM
Microarchitecture	Cortex-A9
Instruction Width	32-bit
Data Width	32-bit
MMU	Yes
Instruction Set	ARMv7-A
Clock Speed	Up to 2 GHz
L1 Cache	32 KB Instruction, 32 KB Data (per core)
Process Technology	40 nm, 28 nm
Floating Point Unit	VFPv3
Pipeline Depth	8 stages
Power Consumption	Low power design