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ARM Cortex A9 User Manual

ARM Cortex A9
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System Control
ARM DDI 0388I Copyright © 2008-2012 ARM. All rights reserved. 4-5
ID073015 Non-Confidential
4.2.1 c0 registers
Table 4-2 shows the CP15 system control registers you can access when CRn is c0.
Table 4-2 c0 register summary
Op1 CRm Op2 Name Type Reset Description
0 c0 0 MIDR RO Product revision
dependant
Main ID Register on page 4-18
1CTR RO
0x83338003
Cache Type Register
2 TCMTR RO
0x00000000
TCM Type Register
3
TLBTR
a
RO - TLB Type Register on page 4-19
5MPIDR RO- Multiprocessor Affinity Register on page 4-19
6REVIDRRO- Revision ID register on page 4-21
c1 0 ID_PFR0 RO
0x00001231
Processor Feature Register 0
1 ID_PFR1 RO
0x00000011
Processor Feature Register 1
2 ID_DFR0 RO
0x00010444
Debug Feature Register 0
3 ID_AFR0 RO
0x00000000
Auxiliary Feature Register 0
4 ID_MMFR0 RO
0x00100103
Memory Model Feature Register 0
5 ID_MMFR1 RO
0x20000000
Memory Model Feature Register 1
6 ID_MMFR2 RO
0x01230000
Memory Model Feature Register 2
7 ID_MMFR3 RO
0x00102111
Memory Model Feature Register 3
c2 0 ID_ISAR0 RO
0x00101111
Instruction Set Attributes Register 0
1 ID_ISAR1 RO
0x13112111
Instruction Set Attributes Register 1
2 ID_ISAR2 RO
0x21232041
Instruction Set Attributes Register 2
3 ID_ISAR3 RO
0x11112131
Instruction Set Attributes Register 3
4 ID_ISAR4 RO
0x00011142
Instruction Set Attributes Register 4
1 c0 0 CCSIDR RO - Cache Size Identification Register on page 4-21
1CLIDR RO
0x09000003
Cache Level ID Register on page 4-22
7AIDR RO
0x00000000
Auxiliary ID Register on page 4-23
2 c0 0 CSSELR RW - Cache Size Selection Register on page 4-24
a. Depends on TLBSIZE. See TLB Type Register on page 4-19.

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ARM Cortex A9 Specifications

General IconGeneral
ArchitectureARMv7-A
Cores1-4
SIMD ExtensionsNEON
ISAARM
MicroarchitectureCortex-A9
Instruction Width32-bit
Data Width32-bit
MMUYes
Instruction SetARMv7-A
Clock SpeedUp to 2 GHz
L1 Cache32 KB Instruction, 32 KB Data (per core)
Process Technology40 nm, 28 nm
Floating Point UnitVFPv3
Pipeline Depth8 stages
Power ConsumptionLow power design

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