ARM Cortex A9 User Manual

System Control
ARM DDI 0388I Copyright © 2008-2012 ARM. All rights reserved. 4-24
ID073015 Non-Confidential
Configurations Available in all configurations.
Attributes See the register summary in Table 4-2 on page 4-5.
To access the Auxiliary Level ID Register, read the CP15 register with:
MRC p15,1,<Rd>,c0,c0,7; Read Auxiliary ID Register
Note
The AIDR is unused in this implementation.
4.3.8 Cache Size Selection Register
The CSSELR characteristics are:
Purpose Selects the current CCSIDR. See the Cache Size Identification Register on
page 4-21.
Usage constraints The CSSELR is:
• only accessible in privileged modes
• banked for Secure and Non-secure states.
Configurations Available in all configurations.
Attributes See the register summary in Table 4-2 on page 4-5.
Figure 4-7 shows the CSSELR bit assignments.
Figure 4-7 CSSELR bit assignments
Table 4-34 shows the CSSELR bit assignments.
To access the CSSELR, read the CP15 register with:
MRC p15, 2,<Rd>, c0, c0, 0; Read CSSELRMCR p15, 2,<Rd>, c0, c0, 0; Write CSSELR
Reserved Level
43 10
InD
31
Table 4-34 CSSELR bit assignments
Bits Name Function
[31:4] - UNP or SBZ.
[3:1] Level Cache level selected, RAZ/WI.
There is only one level of cache in the Cortex-A9 processor so the value for this field is b000.
[0] InD Instruction not Data bit:
0 Data cache
1 Instruction cache.

ARM Cortex A9 Specifications

General

Architecture	ARMv7-A
Cores	1-4
SIMD Extensions	NEON
ISA	ARM
Microarchitecture	Cortex-A9
Instruction Width	32-bit
Data Width	32-bit
MMU	Yes
Instruction Set	ARMv7-A
Clock Speed	Up to 2 GHz
L1 Cache	32 KB Instruction, 32 KB Data (per core)
Process Technology	40 nm, 28 nm
Floating Point Unit	VFPv3
Pipeline Depth	8 stages
Power Consumption	Low power design