ARM Cortex A9 User Manual

System Control
ARM DDI 0388I Copyright © 2008-2012 ARM. All rights reserved. 4-23
ID073015 Non-Confidential
• the Level of Coherency and Level of Unification for the cache
hierarchy.
Usage constraints The CLIDR is:
• only accessible in privileged modes
• common to the Secure and Non-secure states.
Configurations Available in all configurations.
Attributes See the register summary in Table 4-2 on page 4-5.
Figure 4-6 shows the CLIDR bit assignments.
Figure 4-6 CLIDR bit assignments
Table 4-33 shows the CLIDR bit assignments.
To access the CLIDR, read the CP15 register with:
MRC p15, 1,<Rd>, c0, c0, 1; Read CLIDR
4.3.7 Auxiliary ID Register
The AIDR characteristics are:
Purpose Provides implementation-specific information.
Usage constraints The AIDR is:
• only accessible in privileged modes
• common to the Secure and Non-secure states.
L oUIS CL 7 CL 6 CL 5 CL 4 CL 3 CL 2 CL 1
Reserved
31 30 29 27 26 24 23 21 20 18 17 15 14 12 11 10 8 6 5 3 2 0
LoU LoC
Table 4-33 CLIDR bit assignments
Bits Name Function
[31:30] - UNP or SBZ
[29:27] LoU
b001 Level of unification.
[26:24] LoC
b001 Level of coherency.
[23:21] LoUIS
b001 Level of Unification Inner Shareable.
[20:18] CL 7
b000 no cache at CL 7
[17:15] CL 6
b000 no cache at CL 6
[14:12] CL 5
b000 no cache at CL 5
[11:9] CL 4
b000 no cache at CL 4
[8:6] CL 3
b000 no cache at CL 3
[5:3] CL 2
b000 no cache at CL 2
[2:0] CL 1
b011 separate instruction and data caches at CL 1

ARM Cortex A9 Specifications

General

Architecture	ARMv7-A
Cores	1-4
SIMD Extensions	NEON
ISA	ARM
Microarchitecture	Cortex-A9
Instruction Width	32-bit
Data Width	32-bit
MMU	Yes
Instruction Set	ARMv7-A
Clock Speed	Up to 2 GHz
L1 Cache	32 KB Instruction, 32 KB Data (per core)
Process Technology	40 nm, 28 nm
Floating Point Unit	VFPv3
Pipeline Depth	8 stages
Power Consumption	Low power design