ARM Cortex A9 User Manual

System Control
ARM DDI 0388I Copyright © 2008-2012 ARM. All rights reserved. 4-22
ID073015 Non-Confidential
Figure 4-5 CCSIDR bit assignments
Table 4-32 shows how the CSSIDR bit assignments.
To access the CCSIDR, read the CP15 register with:
MRC p15, 1, <Rd>, c0, c0, 0; Read current Cache Size Identification Register
If the CSSELR reads the instruction cache values, then bits [31:28] are b0010.
If the CSSELR reads the data cache values, then bits [31:28] are b0111. See Cache Size
Selection Register on page 4-24.
4.3.6 Cache Level ID Register
The CLIDR characteristics are:
Purpose Identifies:
• the type of cache, or caches, implemented at each level
Line size
31 30 29 28 27 13 12 2 0
NumSets Associativity
WT
WB
RA
WA
Table 4-32 CCSIDR bit assignments
Bits Name Function
[31] WT Indicates support available for Write-Through:
0 Write-Through support not available
1 Write-Through support available.
[30] WB Indicates support available for Write-Back:
0 Write-Back support not available
1 Write-Back support available.
[29] RA Indicates support available for Read-Allocation:
0 Read-Allocation support not available
1 Read-Allocation support available.
[28] WA Indicates support available for Write-Allocation:
0 Write-Allocation support not available
1 Write-Allocation support available.
[27:13] NumSets Indicates number of sets:
0x7F 16KB cache size
0xFF 32KB cache size
0x1FF 64KB cache size.
[12:3] Associativity Indicates number of ways:
b0000000011 Four ways.
[2:0] LineSize Indicates number of words:
b001 Eight words per line.

ARM Cortex A9 Specifications

General

Architecture	ARMv7-A
Cores	1-4
SIMD Extensions	NEON
ISA	ARM
Microarchitecture	Cortex-A9
Instruction Width	32-bit
Data Width	32-bit
MMU	Yes
Instruction Set	ARMv7-A
Clock Speed	Up to 2 GHz
L1 Cache	32 KB Instruction, 32 KB Data (per core)
Process Technology	40 nm, 28 nm
Floating Point Unit	VFPv3
Pipeline Depth	8 stages
Power Consumption	Low power design