ARM Cortex A9 User Manual

Debug
ARM DDI 0388I Copyright © 2008-2012 ARM. All rights reserved. 10-7
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10.5 Debug register descriptions
This section describes the debug registers.
10.5.1 Breakpoint Value Registers
The Breakpoint Value Registers (BVRs) are registers 64-68, at offsets
0x100 - 0x114 . Each BVR
is associated with a Breakpoint Control Register (BCR), for example:
• BVR0 with BCR0
• BVR1 with BCR1.
This pattern continues up to BVR5 with BCR5.
A pair of breakpoint registers, BVRn and BCRn, is called a Breakpoint Register Pair (BRPn).
Table 10-2 shows the BVRs and corresponding BCRs.
The breakpoint value contained in this register corresponds to either an Instruction Virtual
Address (IVA) or a context ID. Breakpoints can be set on:
•an IVA
• a context ID value
• an IVA and context ID pair.
For an IVA and context ID pair, two BRPs must be linked. A debug event is generated when
both the IVA and the context ID pair match at the same time.
Table 10-3 shows how the bit values correspond with the Breakpoint Value Registers functions.
Note
• Only BRP4 and BRP5 support context ID comparison.
• BVR0[1:0], BVR1[1:0], BVR2[1:0], and BVR3[1:0] are Should Be Zero or Preserved on
writes and Read As Zero on reads because these registers do not support context ID
comparisons.
Table 10-2 BVRs and corresponding BCRs
Breakpoint Value Registers Breakpoint Control Registers
Register
number
Offset Name
Register
number
Offset Name
64
0x100 BVR0 80 0x140 BCR0
65
0x104 BVR1 81 0x144 BCR1
66
0x108 BVR2 82 0x148 BCR2
66
0x10C BVR3 83 0x14C BCR3
67
0x110 BVR4 84 0x150 BCR4
68
0x114 BVR5 85 0x154 BCR5
Table 10-3 Breakpoint Value Registers bit functions
Bits Name Description
[31:0] - Breakpoint value. The reset value is 0.

ARM Cortex A9 Specifications

General

Architecture	ARMv7-A
Cores	1-4
SIMD Extensions	NEON
ISA	ARM
Microarchitecture	Cortex-A9
Instruction Width	32-bit
Data Width	32-bit
MMU	Yes
Instruction Set	ARMv7-A
Clock Speed	Up to 2 GHz
L1 Cache	32 KB Instruction, 32 KB Data (per core)
Process Technology	40 nm, 28 nm
Floating Point Unit	VFPv3
Pipeline Depth	8 stages
Power Consumption	Low power design