ARM Cortex A9 User Manual

Performance Monitoring Unit
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11.4 Performance monitoring events
The Cortex-A9 processor implements architectural events shown in Table 11-5. These events
are defined in the ARM Architecture Reference Manual.
For more information about these events see the ARM Architecture Reference Manual.
For events and the corresponding PMUEVENT signals, see Table A-18 on page A-14.
The PMU provides an additional set of Cortex-A9 specific events.
Table 11-5 Implemented architectural events
Number Event
0x00 Software increment
0x01 Instruction cache miss
0x02 Instruction micro TLB miss
0x03 Data cache miss
0x04 Data cache access
0x05 Data micro TLB miss
0x06 Data read
0x07 Data writes
0x08
a
a. This event is not implemented. However, similar functionality is provided by event number 0x68,
Instructions coming out of the core renaming stage. See Table 11-6 on page 11-8
-
0x09 Exception taken
0x0A Exception return
0x0B Write context ID
0x0C Software change of the PC
0x0D Immediate branch
0x0E
b
b. This event is not implemented. However, similar functionality is provided by event number 0x6E,
Predictable function returns. See Table 11-6 on page 11-8
-
0x0F Unaligned load or store
0x10 Branch mispredicted or not predicted
0x11 Cycle count
0x12 Predictable branches

ARM Cortex A9 Specifications

General

Architecture	ARMv7-A
Cores	1-4
SIMD Extensions	NEON
ISA	ARM
Microarchitecture	Cortex-A9
Instruction Width	32-bit
Data Width	32-bit
MMU	Yes
Instruction Set	ARMv7-A
Clock Speed	Up to 2 GHz
L1 Cache	32 KB Instruction, 32 KB Data (per core)
Process Technology	40 nm, 28 nm
Floating Point Unit	VFPv3
Pipeline Depth	8 stages
Power Consumption	Low power design