ARM Cortex A9 User Manual

Programmers Model
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3.5 Security Extensions architecture
Security Extensions enable the construction of a secure software environment. This section
describes the following:
• System boot sequence.
See the ARM Architecture Reference Manual for more information.
3.5.1 System boot sequence
Caution
The Security Extensions enable the construction of an isolated software environment for more
secure execution, depending on a suitable system design around the processor. The technology
does not protect the processor from hardware attacks, and you must ensure that the hardware
containing the reset handling code is appropriately secure.
The processor always boots in the Privileged Supervisor mode in the Secure state, with the NS
bit set to 0. This means that code that does not attempt to use the Security Extensions always
runs in the Secure state. If the software uses both Secure and Non-secure states, the less trusted
software, such as a complex operating system, executes in Non-secure state, and the more
trusted software executes in the Secure state.
The following sequence is expected to be typical use of the Security Extensions:
1. Exit from reset in Secure state.
2. Configure the security state of memory and peripherals. Some memory and peripherals
are accessible only to the software running in Secure state.
3. Initialize the secure operating system. The required operations depend on the operating
system, and typically include initialization of caches, MMU, exception vectors, and
stacks.
4. Initialize Secure Monitor software to handle exceptions that switch execution between the
Secure and Non-Secure operating systems.
5. Optionally lock aspects of the secure state environment against additional configuration.
6. Pass control through the Secure Monitor software to the Non-Secure OS with an
SMC
instruction to enable the Non-secure operating system to initialize. The required
operations depend on the operating system, and typically include initialization of caches,
MMU, exception vectors, and stacks.
The overall security of the secure software depends on the system design, and on the secure
software itself.

ARM Cortex A9 Specifications

General

Architecture	ARMv7-A
Cores	1-4
SIMD Extensions	NEON
ISA	ARM
Microarchitecture	Cortex-A9
Instruction Width	32-bit
Data Width	32-bit
MMU	Yes
Instruction Set	ARMv7-A
Clock Speed	Up to 2 GHz
L1 Cache	32 KB Instruction, 32 KB Data (per core)
Process Technology	40 nm, 28 nm
Floating Point Unit	VFPv3
Pipeline Depth	8 stages
Power Consumption	Low power design