ARM Cortex A9 User Manual

Introduction
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1.6 Configurable options
Table 1-1 shows the configurable options for the Cortex-A9 processor.
The MBIST solution must be configured to match the chosen Cortex-A9 cache sizes. In
addition, the form of the MBIST solution for the RAM blocks in the Cortex-A9 design must be
determined when the processor is implemented.
See the Cortex-A9 MBIST Controller Technical Reference Manual for more information.
Table 1-1 Configurable options for the Cortex-A9 processor
Feature Range of options
Instruction cache size 16KB, 32KB, or 64KB
Data cache size 16KB, 32KB, or 64KB
TLB entries 64, 128, 256 or 512 entries
BTAC entries 512, 1024, 2048 or 4096 entries
GHB descriptors 1024, 2048, 4096, 8192 or 16384 descriptors
Instruction micro TLB 32 or 64 entries
Jazelle Architecture Extension Full or trivial
Media Processing Engine with NEON technology
Included or not
a
a. The MPE and FPU RTL options are mutually exclusive. If you choose the MPE option, the MPE is
included along with its VFPv3-D32 FPU, and the FPU RTL option is not available in this case. When
the MPE RTL option is not implemented, you can implement the VFPv3-D16 FPU by choosing the
FPU RTL option.
FPU
Included or not
a
PTM interface Included or not
Wrappers for power off and dormant modes Included or not
Support for parity error detection
b
b. The Cortex A9 processor does not support Parity error detection on the GHB RAMs, for GHB
configurations of 8192 and 16384 entries.
-
Preload Engine Included or not
Preload Engine FIFO size
c
c. Only when the design includes the Preload Engine.
16, 8, or 4 entries
ARM_BIST Included or not
USE DESIGNWARE Use or not

ARM Cortex A9 Specifications

General

Architecture	ARMv7-A
Cores	1-4
SIMD Extensions	NEON
ISA	ARM
Microarchitecture	Cortex-A9
Instruction Width	32-bit
Data Width	32-bit
MMU	Yes
Instruction Set	ARMv7-A
Clock Speed	Up to 2 GHz
L1 Cache	32 KB Instruction, 32 KB Data (per core)
Process Technology	40 nm, 28 nm
Floating Point Unit	VFPv3
Pipeline Depth	8 stages
Power Consumption	Low power design