EasyManuals Logo

ARM Cortex A9 User Manual

ARM Cortex A9
213 pages
To Next Page IconTo Next Page
To Next Page IconTo Next Page
To Previous Page IconTo Previous Page
To Previous Page IconTo Previous Page
Page #144 background imageLoading...
Page #144 background image
Debug
ARM DDI 0388I Copyright © 2008-2012 ARM. All rights reserved. 10-5
ID073015 Non-Confidential
10.4 Debug register summary
You can access the debug registers:
through the CP14 interface. The debug registers are mapped to coprocessor instructions.
through the APB using the relevant offset when PADDRDBG[12]=0, with the following
exceptions:
DBGRAR
—DBGSAR
DBGSCR-int
DBGTR-int.
External views of DBSCR and DBGTR are accessible through memory-mapped APB access.
Table 10-1 shows the CP14 interface registers. All other registers are described in the ARM
Architecture Reference Manual.
Table 10-1 CP14 Debug register summary
Register
number
Offset CRn Op1 CRm Op2 Name Type Description
0
0x000
c0 0 c0 0
DBGDIDR
ab
RO See the ARM Architecture Reference
Manual
-- c10c00
DBGDRAR
a
RO
-- c20c00
DBGDSAR
a
RO
-- c00c10
DBGDSCRint
ab
RO
5- c00c50
DBGDTRRXint
a
RO
DBGDTRTXint
a
WO Reserved
6
0x018
c0 0 c6 0 DBGWFAR RW Use of DBGWFAR is deprecated in
the ARMv7 architecture, because
watchpoints are synchronous
7
0x01C
c0 0 c7 0 DBGVCR RW See the ARM Architecture Reference
Manual
8 - - - - - - - Reserved
9
0x024
c0 0 c9 0 DBGECR RAZ/WI Not implemented
10
0x028
c0 0 c10 0 DBGDSCCR RAZ/WI
11
0x02C
c0 0 c11 0 DBGDSMCR RAZ/WI
12-31 - - - - - - - Reserved
32
0x080
c0 0 c0 2 DBGDTRRXext RW See the ARM Architecture Reference
Manual
33
0x084
c0 0 c1 2 DBGITR WO
33
0x084
c0 0 c1 2 DBGPCSR RO
34
0x088
c0 0 c2 2 DBGDSCRext RW
35
0x08C
c0 0 c3 2 DBGDTRTXext RW
36
0x090
c0 0 c4 2 DBGDRCR WO See the ARM Architecture Reference
Manual

Table of Contents

Questions and Answers:

Question and Answer IconNeed help?

Do you have a question about the ARM Cortex A9 and is the answer not in the manual?

ARM Cortex A9 Specifications

General IconGeneral
ArchitectureARMv7-A
Cores1-4
SIMD ExtensionsNEON
ISAARM
MicroarchitectureCortex-A9
Instruction Width32-bit
Data Width32-bit
MMUYes
Instruction SetARMv7-A
Clock SpeedUp to 2 GHz
L1 Cache32 KB Instruction, 32 KB Data (per core)
Process Technology40 nm, 28 nm
Floating Point UnitVFPv3
Pipeline Depth8 stages
Power ConsumptionLow power design

Related product manuals