Debug
ARM DDI 0388I Copyright © 2008-2012 ARM. All rights reserved. 10-6
ID073015 Non-Confidential
37-63 - - - - - Reserved - Reserved
64-68
0x100
-
0x114
c0 0 c0-c5 4 DBGBVRn RW Breakpoint Value Registers on
page 10-7
69-79- ---- - - Reserved
80-85
0x140
-
0x154
c0 0 c0-c5 5 DBGBCRn RW Breakpoint Control Registers on
page 10-8
86-95 - - - Reserved
96-99
0x180
-
0x18C
c0 0 c0-c3 6 DBGWVRn RW Watchpoint Value Registers on
page 10-10
100-111- ---- - - Reserved
112-115
0x1C0
-
0x1CC
c0 0 c0-c3 7 DBGWCRn RW Watchpoint Control Registers on
page 10-11
116-191 - - - - - - - Reserved
192
0x300
c1 0 c0 4 DBGOSLAR RAZ/WI Not implemented
193
0x304
c1 0 c1 4 DBGOSLSR RAZ/WI
194
0x308
c1 0 c2 4 DBGOSSRR RAZ/WI
195 - - - - - - - Reserved
196
0x310
c1 0 c4 4 DBGPRCR RO See the ARM Architecture Reference
Manual
197
0x314
c1 0 c5 4 DBGPRSR RO
198-831 - - - - - - - Reserved
832-895
0xD00
-
0xDFC
---- Processor ID
Registers
c
RO Identification Registers on page 4-12
896-927
0xE00-
0xE7C
---- - - Reserved
928-959
0xE80
-
0xEFC
c7 0 c0 15, 2-3 - RAZ/WI Reserved
960-1023
0xF00
-
0xFFC
---- Debug
Management
Registers
- Debug management registers on
page 10-13
a. Baseline CP14 interface. This register also has an external view through the memory-mapped interface and the CP14 interface.
b. Accessible in User mode if bit [12] of the DBGSCR is clear. Also accessible in privileged modes.
c. The Extended CP14 interface
MRC
and
MCR
instructions that map to these registers are UNDEFINED in User mode and UNPREDICTABLE in
privileged modes. You must use the CP15 interface to access these registers.
Table 10-1 CP14 Debug register summary (continued)
Register
number
Offset CRn Op1 CRm Op2 Name Type Description
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