ARM Cortex A9 User Manual

Debug
ARM DDI 0388I Copyright © 2008-2012 ARM. All rights reserved. 10-11
ID073015 Non-Confidential
The watchpoint value contained in the WVR always corresponds to a Data Virtual Address
(DVA) and can be set either on:
•a DVA
• a DVA and context ID pair.
For a DVA and context ID pair, a WRP and a BRPs with context ID comparison capability must
be linked. A debug event is generated when both the DVA and the context ID pair match
simultaneously. Table 10-7 shows how the bit values correspond with the Watchpoint Value
Registers functions.
10.5.4 Watchpoint Control Registers
The WCRs contain the necessary control bits for setting:
• watchpoints
• linked watchpoints.
Figure 10-4 shows the WCRs bit assignments.
Figure 10-4 WCR Register bit assignments
Table 10-8 shows the WCRs bit assignments.
Table 10-7 Watchpoint Value Registers bit functions
Bits Name Description
[31:2] - Watchpoint address
[1:0] - RAZ on reads, SBZP on writes
Reserved
Linked BRP L/S W
Reserved
Watchpoint
address mask
31
21
20 19 16 15 5 3 2 1
ESP
24
4014 13
29 28
23
Secure state access control
12
RAZ,SBZP on writes
89
Reserved
Byte
address
select
Table 10-8 WCR Register bit assignments
Bits Name Description
[31:29] - RAZ on reads, SBZP on writes.
[28:24] Watchpoint
address
mask
Watchpoint address mask.
[23:21] - RAZ on reads, SBZP on writes.
[20] E Enable linking bit:
0 Linking disabled.
1 Linking enabled.
When this bit is set, this watchpoint is linked with the context ID holding BRP selected by the linked BRP
field.
[19:16] Linked
BRP
Linked BRP number. The binary number encoded here indicates a context ID holding BRP to link this WRP
with. If this WRP is linked to a BRP that is not configured for linked context ID matching, it is
UNPREDICTABLE whether a watchpoint debug event is generated.

ARM Cortex A9 Specifications

General

Architecture	ARMv7-A
Cores	1-4
SIMD Extensions	NEON
ISA	ARM
Microarchitecture	Cortex-A9
Instruction Width	32-bit
Data Width	32-bit
MMU	Yes
Instruction Set	ARMv7-A
Clock Speed	Up to 2 GHz
L1 Cache	32 KB Instruction, 32 KB Data (per core)
Process Technology	40 nm, 28 nm
Floating Point Unit	VFPv3
Pipeline Depth	8 stages
Power Consumption	Low power design