ARM Cortex A9 User Manual

Debug
ARM DDI 0388I Copyright © 2008-2012 ARM. All rights reserved. 10-10
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Table 10-5 shows the meaning of the BVR as specified by BCR bits [22:20].
10.5.3 Watchpoint Value Registers
The Watchpoint Value Registers (WVRs) are registers 96-99, at offsets
0x180 - 0x18C . Each WVR
is associated with a Watchpoint Control Register (WCR), for example:
• WVR0 with WCR0
• WVR1 with WCR1.
This pattern continues up to WVR3 with WCR3.
Table 10-6 shows the WVRs and corresponding WCRs.
A pair of watchpoint registers, WVRn and WCRn, is called a Watchpoint Register Pair
(WRPn).
Table 10-5 Meaning of BVR as specified by BCR bits [22:20]
BCR[22:20] Meaning
b000 The corresponding BVR[31:2] is compared against the IVA bus and the state of the processor against this BCR. It
generates a breakpoint debug event on a joint IVA and state match.
b001 The corresponding BVR[31:2] is compared against the IVA bus and the state of the processor against this BCR. This
BRP is linked with the one indicated by BCR[19:16] linked BRP field. They generate a breakpoint debug event on a
joint IVA, context ID, and state match.
b010 The corresponding BVR[31:0] is compared against CP15 Context ID Register, c13 and the state of the processor
against this BCR. This BRP is not linked with any other one. It generates a breakpoint debug event on a joint context
ID and state match. For this BRP, BCR[8:5] must be set to b1111. Otherwise, it is UNPREDICTABLE whether a
breakpoint debug event is generated.
b011 The corresponding BVR[31:0] is compared against CP15 Context ID Register, c13. This BRP links another BRP (of
the BCR[21:20]=b01 type), or WRP (with WCR[20]=b1). They generate a breakpoint or watchpoint debug event on
a joint IVA or DVA and context ID match. For this BRP, BCR[8:5] must be set to b1111, BCR[15:14] must be set to
b00, and BCR[2:1] must be set to b11. Otherwise, it is
UNPREDICTABLE whether a breakpoint debug event is generated.
b100 The corresponding BVR[31:2] and BCR[8:5] are compared against the IVA bus and the state of the processor against
this BCR. It generates a breakpoint debug event on a joint IVA mismatch and state match.
b101 The corresponding BVR[31:2] and BCR[8:5] are compared against the IVA bus and the state of the processor against
this BCR. This BRP is linked with the one indicated by BCR[19:16] linked BRP field. It generates a breakpoint debug
event on a joint IVA mismatch, state and context ID match.
b11x Reserved. The behavior is UNPREDICTABLE.
Table 10-6 WVRs and corresponding WCRs
Watchpoint Value Registers Watchpoint Control Registers
Register
number
Offset Name
Register
number
Offset Name
96
0x180 WVR0 112 0x1C0 WCR0
97
0x184 WVR1 113 0x1C4 WCR1
98
0x188 WVR2 114 0x1C8 WCR2
99
0x18C WVR3 115 0x1DC WCR3

ARM Cortex A9 Specifications

General

Architecture	ARMv7-A
Cores	1-4
SIMD Extensions	NEON
ISA	ARM
Microarchitecture	Cortex-A9
Instruction Width	32-bit
Data Width	32-bit
MMU	Yes
Instruction Set	ARMv7-A
Clock Speed	Up to 2 GHz
L1 Cache	32 KB Instruction, 32 KB Data (per core)
Process Technology	40 nm, 28 nm
Floating Point Unit	VFPv3
Pipeline Depth	8 stages
Power Consumption	Low power design