ARM Cortex A9 User Manual

Introduction
ARM DDI 0388I Copyright © 2008-2012 ARM. All rights reserved. 1-2
ID073015 Non-Confidential
1.1 About the Cortex-A9 processor
The Cortex-A9 processor is a high-performance, low-power, ARM macrocell with an L1 cache
subsystem that provides full virtual memory capabilities. The Cortex-A9 processor implements
the ARMv7-A architecture and runs 32-bit ARM instructions, 16-bit and 32-bit Thumb
instructions, and 8-bit Java bytecodes in Jazelle state.
Figure 1-1 shows a Cortex-A9 uniprocessor in a design with a PL390 Interrupt Controller and
an L2C-310 L2 Cache Controller,
Figure 1-1 Cortex-A9 uniprocessor system
1.1.1 Data engine
The design can include a data engine. The following sections describe the data engine options:
• Media Processing Engine
• Floating-Point Unit.
Media Processing Engine
The optional NEON Media Processing Engine (MPE) is the ARM Advanced Single Instruction
Multiple Data (SIMD) media processing engine extension to the ARMv7-A architecture. It
provides support for integer and floating-point vector operations. NEON MPE can accelerate
the performance of multimedia applications such as 3-D graphics and image processing.
When implemented, the NEON MPE option extends the processor functionality to provide
support for the ARMv7 Advanced SIMD and VFPv3 D-32 instruction sets.
See the Cortex-A9 NEON Media Processing Engine Technical Reference Manual.
Floating-Point Unit
When the design does not include the optional MPE, you can include the optional ARMv7
VFPv3-D16 FPU, without the Advanced SIMD extensions. It provides trapless execution and
is optimized for scalar operation. The Cortex-A9 FPU hardware does not support the deprecated
VFP short vector feature. Attempts to execute VFP data-processing instructions when the
Cortex-A9
uniprocessor
Debug
interface
Performance
Monitor Unit
(PMU)
Generic
Interrupt
Controller
(GIC)
Data Engine
(optional)
Either MPE
or FPU
Program
Trace
interface
CoreLink Level 2 Cache Controller (L2C-310)
CoreSight
trace delivery infrastructure
nFIQ
nIRQ
Instruction
interface
Data
interface
APB
Preload
Engine
(optional)
Events

ARM Cortex A9 Specifications

General

Architecture	ARMv7-A
Cores	1-4
SIMD Extensions	NEON
ISA	ARM
Microarchitecture	Cortex-A9
Instruction Width	32-bit
Data Width	32-bit
MMU	Yes
Instruction Set	ARMv7-A
Clock Speed	Up to 2 GHz
L1 Cache	32 KB Instruction, 32 KB Data (per core)
Process Technology	40 nm, 28 nm
Floating Point Unit	VFPv3
Pipeline Depth	8 stages
Power Consumption	Low power design