ARM Cortex A9 User Manual

Introduction
ARM DDI 0388I Copyright © 2008-2012 ARM. All rights reserved. 1-3
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FPSCR.LEN field is non-zero result in the FPSCR.DEX bit being set and a synchronous
Undefined Instruction exception being taken. You can use software to emulate the short vector
feature, if required.
See the Cortex-A9 Floating-Point Unit Technical Reference Manual.
1.1.2 System design components
This section describes the PrimeCell components in:
• PrimeCell Generic Interrupt Controller
• CoreLink Level 2 Cache Controller (L2C-310).
PrimeCell Generic Interrupt Controller
A generic interrupt controller such as the PrimeCell Generic Interrupt Controller (PL390) can
be attached to the Cortex-A9 uniprocessor. The Cortex-A9 MPCore contains an integrated
interrupt controller that shares the same programmers model as the PL390 although there are
implementation-specific differences.
See the Cortex-A9 MPCore Technical Reference Manual for a description of the Cortex-A9
MPCore Interrupt Controller.
CoreLink Level 2 Cache Controller (L2C-310)
The addition of an on-chip secondary cache, also referred to as a Level 2 or L2 cache, is a
recognized method of improving the performance of ARM-based systems when significant
memory traffic is generated by the processor. The CoreLink Level 2 Cache Controller reduces
the number of external memory accesses and has been optimized for use with Cortex-A9
processors and Cortex-A9 MPCore processors.

ARM Cortex A9 Specifications

General

Architecture	ARMv7-A
Cores	1-4
SIMD Extensions	NEON
ISA	ARM
Microarchitecture	Cortex-A9
Instruction Width	32-bit
Data Width	32-bit
MMU	Yes
Instruction Set	ARMv7-A
Clock Speed	Up to 2 GHz
L1 Cache	32 KB Instruction, 32 KB Data (per core)
Process Technology	40 nm, 28 nm
Floating Point Unit	VFPv3
Pipeline Depth	8 stages
Power Consumption	Low power design