ARM Cortex A9 User Manual

Introduction
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1.3 Compliance
The Cortex-A9 processor complies with, or implements, the specifications described in:
• ARM architecture
• Advanced Microcontroller Bus Architecture
• Program Flow Trace architecture
• Debug architecture
• Generic Interrupt Controller architecture
This TRM complements architecture reference manuals, architecture specifications, protocol
specifications, and relevant external standards. It does not duplicate information from these
sources.
1.3.1 ARM architecture
The Cortex-A9 processor implements the ARMv7-A architecture profile that includes the
following architecture extensions:
• Advanced Single Instruction Multiple Data (SIMD) architecture extension for integer and
floating-point vector operations
• Vector Floating-Point version 3 (VFPv3) architecture extension for floating-point
computation that is fully compliant with the IEEE 754 standard
• Security Extensions for enhanced security
• Multiprocessing Extensions for multiprocessing functionality.
See the ARM Architecture Reference Manual, ARMv7-A and ARMv7-R edition.
1.3.2 Advanced Microcontroller Bus Architecture
The Cortex-A9 processor complies with the AMBA 3 protocol. See the AMBA AXI Protocol
Specification.
1.3.3 Program Flow Trace architecture
The Cortex-A9 processor implements the Program Trace Macrocell (PTM) based on the
Program Flow Trace (PFT) v1.0 architecture. See the CoreSight Program Flow Trace
Architecture Specification.
1.3.4 Debug architecture
The Cortex-A9 processor implements the ARMv7 Debug architecture that includes support for
Security Extensions and CoreSight. See the CoreSight Architecture Specification.
1.3.5 Generic Interrupt Controller architecture
The Cortex-A9 processor implements the ARM Generic Interrupt Controller (GIC) v1.0
architecture.

ARM Cortex A9 Specifications

General

Architecture	ARMv7-A
Cores	1-4
SIMD Extensions	NEON
ISA	ARM
Microarchitecture	Cortex-A9
Instruction Width	32-bit
Data Width	32-bit
MMU	Yes
Instruction Set	ARMv7-A
Clock Speed	Up to 2 GHz
L1 Cache	32 KB Instruction, 32 KB Data (per core)
Process Technology	40 nm, 28 nm
Floating Point Unit	VFPv3
Pipeline Depth	8 stages
Power Consumption	Low power design