ARM Cortex A9 User Manual

Signal Descriptions
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A.8 Performance monitoring signals
Table A-17 shows the performance monitoring signals.
Table A-18 gives the correlation between PMUEVENT signals and their event numbers.
Table A-17 Performance monitoring signals
Name I/O Destination Description
PMUEVENT[57:0] OPTM or external
monitoring unit
PMU event bus. See Table A-18.
PMUIRQ O PMU interrupt signal.
PMUSECURE O Gives the status of the Cortex-A9 processor:
0 In Non-secure state.
1 In Secure state.
This signal does not provide input to CoreSight trace delivery infrastructure.
PMUPRIV O Gives the status of the Cortex-A9 processor:
0 In User mode.
1 In Privileged mode.
This signal does not provide input to CoreSight trace delivery infrastructure.
Table A-18 Event signals and event numbers
Name Event number Description
PMUEVENT[0]
0x00 Software increment
PMUEVENT[1]
0x01 Instruction cache miss
PMUEVENT[2]
0x02 Instruction micro TLB miss
PMUEVENT[3]
0x03 Data cache miss
PMUEVENT[4]
0x04 Data cache access
PMUEVENT[5]
0x05 Data micro TLB miss
PMUEVENT[6]
0x06 Data read
PMUEVENT[7]
0x07 Data writes
-
0x08
Unused
a
PMUEVENT[8] 0x68 b00 No instructions renamed.
b01 One instruction renamed.
b10 Two instructions renamed.
PMUEVENT[9]
PMUEVENT[10]
0x09 Exception taken
PMUEVENT[11]
0x0A Exception returns
PMUEVENT[12]
0x0B Write context ID
PMUEVENT[13]
0x0C Software change of PC
PMUEVENT[14]
0x0D Immediate branch
-
0x0E
Unused
b
PMUEVENT[15] 0x6E
Predictable function return
b

ARM Cortex A9 Specifications

General

Architecture	ARMv7-A
Cores	1-4
SIMD Extensions	NEON
ISA	ARM
Microarchitecture	Cortex-A9
Instruction Width	32-bit
Data Width	32-bit
MMU	Yes
Instruction Set	ARMv7-A
Clock Speed	Up to 2 GHz
L1 Cache	32 KB Instruction, 32 KB Data (per core)
Process Technology	40 nm, 28 nm
Floating Point Unit	VFPv3
Pipeline Depth	8 stages
Power Consumption	Low power design