Signal Descriptions
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Read data channel signals
Table A-15 shows the AXI read data signals for AXI Master1.
AXI Master1 Clock enable signals
Table A-16 shows the AXI Master1 clock enable signals.
See Chapter 8 Level 2 Memory Interface.
Table A-15 AXI-R signals for AXI Master1
Name I/O Source or destination Description
RVALIDM1 I AXI system devices Read valid
RDATAM1[63:0] IRead data
RRESPM1[1:0] I Read response
RLASTM1 I Read last indication
RIDM1[5:0] IRead ID
RREADYM1 O Read ready
Table A-16 Clock enable signal for AXI Master1
Name I/O Source Description
ACLKENM1 IClock
controller
Clock enable for the AXI bus that enables the AXI interface to operate at integer ratios of the
system clock.
See Clocking and resets on page 2-6.
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