ARM Cortex A9 User Manual

Signal Descriptions
ARM DDI 0388I Copyright © 2008-2012 ARM. All rights reserved. A-12
ID073015 Non-Confidential
Read address channel signals for AXI Master1
Table A-14 shows the AXI read address channel signals for AXI Master1.
Table A-14 Read address channel signals for AXI Master1
Name I/O Destination Description
ARADDRM1[31:0] O AXI system devices Address.
ARBURSTM1[1:0] O Burst type:
b001 INCR incrementing burst.
b010 WRAP Wrapping burst.
ARCACHEM1[3:0] O Cache type giving additional information about cacheable characteristics.
ARIDM1[5:0] O Request ID.
ARLENM1[3:0] O The number of data transfers that can occur within each burst.
ARLOCKM1[1:0] O Lock type:
b00 Normal access.
ARPROTM1[2:0] O Protection type.
ARREADYM1 I Address ready.
ARSIZEM1[1:0] O AXI system devices Burst size:
b000 8-bit transfer.
b001 16-bit transfer.
b010 32-bit transfe.r
b011 64-bit transfer.
ARUSERM1[4:0] O [4:1] = Inner attributes
b0000 Strongly Ordered.
b0001 Device.
b0011 Normal Memory Non-Cacheable.
b0110 Write-Through.
b0111 Write-Back no Write-Allocate.
b1111 Write-Back Write-Allocate.
[0] = Shared.
ARVALIDM1 O Address valid.

ARM Cortex A9 Specifications

General

Architecture	ARMv7-A
Cores	1-4
SIMD Extensions	NEON
ISA	ARM
Microarchitecture	Cortex-A9
Instruction Width	32-bit
Data Width	32-bit
MMU	Yes
Instruction Set	ARMv7-A
Clock Speed	Up to 2 GHz
L1 Cache	32 KB Instruction, 32 KB Data (per core)
Process Technology	40 nm, 28 nm
Floating Point Unit	VFPv3
Pipeline Depth	8 stages
Power Consumption	Low power design