ARM Cortex A9 User Manual

Signal Descriptions
ARM DDI 0388I Copyright © 2008-2012 ARM. All rights reserved. A-18
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A.10 Parity signal
Table A-20 shows the parity signal. This signal is present only if parity is defined. See Parity
error support on page 7-12.
Table A-20 Parity signal
Name I/O Destination Description
PARITYFAIL[7:0] O Parity monitoring device Parity output pin from the RAM arrays:
0 No parity fail.
1 Parity fail.
Bit [7] BTAC parity error
Bit [6] GHB parity error
Bit [5] instruction tag RAM parity error
Bit [4] instruction data RAM parity error
Bit [3] main TLB parity error
Bit [2] data outer RAM parity error
Bit [1] data tag RAM parity error
Bit [0] data data RAM parity error.

ARM Cortex A9 Specifications

General

Architecture	ARMv7-A
Cores	1-4
SIMD Extensions	NEON
ISA	ARM
Microarchitecture	Cortex-A9
Instruction Width	32-bit
Data Width	32-bit
MMU	Yes
Instruction Set	ARMv7-A
Clock Speed	Up to 2 GHz
L1 Cache	32 KB Instruction, 32 KB Data (per core)
Process Technology	40 nm, 28 nm
Floating Point Unit	VFPv3
Pipeline Depth	8 stages
Power Consumption	Low power design