ARM Cortex A9 - Parity Signal; A.10 Parity Signal

Signal Descriptions
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A.10 Parity signal
Table A-20 shows the parity signal. This signal is present only if parity is defined. See Parity
error support on page 7-12.
Table A-20 Parity signal
Name I/O Destination Description
PARITYFAIL[7:0] O Parity monitoring device Parity output pin from the RAM arrays:
0 No parity fail.
1 Parity fail.
Bit [7] BTAC parity error
Bit [6] GHB parity error
Bit [5] instruction tag RAM parity error
Bit [4] instruction data RAM parity error
Bit [3] main TLB parity error
Bit [2] data outer RAM parity error
Bit [1] data tag RAM parity error
Bit [0] data data RAM parity error.