ARM Cortex A9 User Manual

ARM DDI 0388I Copyright © 2008-2012 ARM. All rights reserved. 8-1
ID073015 Non-Confidential
Chapter 8
Level 2 Memory Interface
This chapter describes the L2 memory interface. It contains the following sections:
• About the Cortex-A9 L2 interface on page 8-2
• Optimized accesses to the L2 memory interface on page 8-7
• STRT instructions on page 8-9.

ARM Cortex A9 Specifications

General

Architecture	ARMv7-A
Cores	1-4
SIMD Extensions	NEON
ISA	ARM
Microarchitecture	Cortex-A9
Instruction Width	32-bit
Data Width	32-bit
MMU	Yes
Instruction Set	ARMv7-A
Clock Speed	Up to 2 GHz
L1 Cache	32 KB Instruction, 32 KB Data (per core)
Process Technology	40 nm, 28 nm
Floating Point Unit	VFPv3
Pipeline Depth	8 stages
Power Consumption	Low power design