ARM Cortex A9 User Manual

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Level 1 Memory System

ID073015 Non-Confidential

Note

The Cortex-A9 does not provide parity error detection support on the GHB RAMs, for GHB

configurations of 8192 and 16384 entries.

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General

Architecture	ARMv7-A
Cores	1-4
SIMD Extensions	NEON
ISA	ARM
Microarchitecture	Cortex-A9
Instruction Width	32-bit
Data Width	32-bit
MMU	Yes
Instruction Set	ARMv7-A
Clock Speed	Up to 2 GHz
L1 Cache	32 KB Instruction, 32 KB Data (per core)
Process Technology	40 nm, 28 nm
Floating Point Unit	VFPv3
Pipeline Depth	8 stages
Power Consumption	Low power design