ARM Cortex A9 User Manual

Signal Descriptions
ARM DDI 0388I Copyright © 2008-2012 ARM. All rights reserved. A-15
ID073015 Non-Confidential
PMUEVENT[16] 0x0F Unaligned
PMUEVENT[17]
0x10 Branch mispredicted or not predicted
Not exported
0x11 Cycle count
PMUEVENT[18]
0x12 Predictable branches
PMUEVENT[19]
0x40 Java bytecode
PMUEVENT[20]
0x41 Software Java bytecode
PMUEVENT[21]
0x42 Jazelle backward branch
PMUEVENT[22]
0x50
Coherent linefill miss
c
PMUEVENT[23] 0x51
Coherent linefill hit
c
PMUEVENT[24] 0x60 Instruction cache dependent stall
PMUEVENT[25]
0x61 Data cache dependent stall
PMUEVENT[26]
0x62 Main TLB miss stall
PMUEVENT[27]
0x63 STREX passed
PMUEVENT[28]
0x64 STREX failed
PMUEVENT[29]
0x65 Data eviction
PMUEVENT[30]
0x66 Issue does not dispatch any instruction
PMUEVENT[31]
0x67 Issue is empty
PMUEVENT[32]
0x70 Main Execution Unit pipe
PMUEVENT[33]
0x71 Second Execution Unit pipe
PMUEVENT[34]
0x72 Load/Store pipe
PMUEVENT[35]
0x73 b00 No floating-point instruction renamed.
b01 One floating-point instruction renamed.
b10 Two floating-point instructions renamed.
PMUEVENT[36]
PMUEVENT[37] 0x74
b00 No NEON instructions renamed.
b01 One NEON instruction renamed.
b10 Two NEON instructions renamed.
PMUEVENT[38]
PMUEVENT[39]
0x80 PLD stall
PMUEVENT[40]
0x81 Write stall
PMUEVENT[41]
0x82 Instruction main TLB miss stall
PMUEVENT[42]
0x83 Data main TLB miss stall
PMUEVENT[43]
0x84 Instruction micro TLB miss stall
PMUEVENT[44]
0x85 Data micro TLB miss stall
PMUEVENT[45]
0x86 DMB stall
PMUEVENT[46]
0x8A Integer core clock enabled
Table A-18 Event signals and event numbers (continued)
Name Event number Description

ARM Cortex A9 Specifications

General

Architecture	ARMv7-A
Cores	1-4
SIMD Extensions	NEON
ISA	ARM
Microarchitecture	Cortex-A9
Instruction Width	32-bit
Data Width	32-bit
MMU	Yes
Instruction Set	ARMv7-A
Clock Speed	Up to 2 GHz
L1 Cache	32 KB Instruction, 32 KB Data (per core)
Process Technology	40 nm, 28 nm
Floating Point Unit	VFPv3
Pipeline Depth	8 stages
Power Consumption	Low power design