ARM Cortex A9 User Manual

Signal Descriptions
ARM DDI 0388I Copyright © 2008-2012 ARM. All rights reserved. A-16
ID073015 Non-Confidential
See Cortex-A9 specific events on page 11-8.
PMUEVENT[47] 0x8B Data engine clock enabled
PMUEVENT[48]
0x90 ISB
PMUEVENT[49]
0x91 DSB
PMUEVENT[50]
0x92 DMB
PMUEVENT[51]
0x93 External interrupt
PMUEVENT[52] 0xA0 PLE cache line request completed
PMUEVENT[53] 0xA1 PLE cache line request skipped
PMUEVENT[54] 0xA2 PLE FIFO Flush
PMUEVENT[55] 0xA3 PLE request completed
PMUEVENT[56] 0xA4 PLE FIFO Overflow
PMUEVENT[57] 0xA5 PLE request programmed
a. Not generated by Cortex-A9 processors. Replaced by the similar event 0x68 .
b. Not generated by Cortex-A9 processors. Replaced by the similar event
0x6E .
c. Used in multiprocessor configurations.
Table A-18 Event signals and event numbers (continued)
Name Event number Description

ARM Cortex A9 Specifications

General

Architecture	ARMv7-A
Cores	1-4
SIMD Extensions	NEON
ISA	ARM
Microarchitecture	Cortex-A9
Instruction Width	32-bit
Data Width	32-bit
MMU	Yes
Instruction Set	ARMv7-A
Clock Speed	Up to 2 GHz
L1 Cache	32 KB Instruction, 32 KB Data (per core)
Process Technology	40 nm, 28 nm
Floating Point Unit	VFPv3
Pipeline Depth	8 stages
Power Consumption	Low power design