Debug
ARM DDI 0388I Copyright © 2008-2012 ARM. All rights reserved. 10-8
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• The context ID value for a BVR to match with is given by the contents of the CP15
Context ID Register.
10.5.2 Breakpoint Control Registers
The BCR is a read/write register that contains the necessary control bits for setting:
• breakpoints
• linked breakpoints.
Figure 10-3 shows the BCRs bit assignments.
Figure 10-3 BCR Register bit assignments
Table 10-4 shows the BCRs bit assignments.
Reserved
M Linked BRP Reserved
Byte
address
select
Secure state access control
Breakpoint
address mask
Reserved Reserved
B
31 29 28 24 23 22 20 19 16 15 14 13 9 8 5 4 3 2 1 0
SP
Table 10-4 BCR Register bit assignments
Bits Name Description
[31:29] - RAZ on reads, SBZP on writes.
[28:24] Breakpoint
address mask
Breakpoint address mask. RAZ/WI.
b00000
No mask.
[23] - RAZ on reads, SBZP on writes.
[22:20] M Meaning of BVR:
b000
Instruction virtual address match.
b001
Linked instruction virtual address match.
b010
Unlinked context ID.
b011
Linked context ID.
b100
Instruction virtual address mismatc.h
b101 Linked instruction virtual address mismatch.
b11x
Reserved.
BCR0[21], BCR1[21], BCR2[21], and BCR3[21] are RAZ on reads because these registers do not have
context ID comparison capability.
[19:16] Linked BRP Linked BRP number. The binary number encoded here indicates another BRP to link this one with.
• if a BRP is linked with itself, it is UNPREDICTABLE whether a breakpoint debug event is generated
• if this BRP is linked to another BRP that is not configured for linked context ID matching, it is
UNPREDICTABLE whether a breakpoint debug event is generated.
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