System Control
ARM DDI 0388I Copyright © 2008-2012 ARM. All rights reserved. 4-25
ID073015 Non-Confidential
4.3.9 System Control Register
The SCTLR characteristics are:
Purpose Provides control and configuration of:
• memory alignment and endianness
• memory protection and fault behavior
• MMU and cache enables
• interrupts and behavior of interrupt latency
• location for exception vectors
• program flow prediction.
Usage constraints The SCTLR is:
• Only accessible in privileged modes.
• Partially banked. Table 4-35 shows banked and secure modify only
bits.
Configurations Available in all configurations.
Attributes See the register summary in Table 4-3 on page 4-6.
Figure 4-8 shows the SCTLR bit assignments.
Figure 4-8 SCTLR bit assignments
Table 4-35 shows the SCTLR bit assignments.
31 30 29 28 27 26 25 24 14 13 12 11 10 3 2 1 0
MI
NMFI
Reserved
Reserved
ReservedVZ CA
23 22 21 20 19 9
SW bit
18 17 16 15
RR bit
TE
AFE
TRE
EE HA
Table 4-35 SCTLR bit assignments
Bits Name Access Function
[31] - - SBZ.
[30] TE Banked Thumb exception enable:
0 Exceptions, including reset, are handled in ARM state
1 Exceptions, including reset, are handled in Thumb state.
The TEINIT signal defines the reset value.
[29] AFE Banked Access Flag enable bit:
0 Full access permissions behavior. This is the reset value.
The software maintains binary compatibility with ARMv6K behavior.
1 Simplified access permissions behavior.
The Cortex-A9 processor redefines the AP[0] bit as an access flag.
The TLB must be invalidated after changing the AFE bit.
[28] TRE Banked This bit controls the TEX remap functionality in the MMU:
0 TEX remap disabled. This is the reset value.
1 TEX remap enabled.
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