ARM Cortex A9 User Manual

System Control
ARM DDI 0388I Copyright © 2008-2012 ARM. All rights reserved. 4-6
ID073015 Non-Confidential
4.2.2 c1 registers
Table 4-3 shows the CP15 system control registers you can access when CRn is c1.
4.2.3 c2 registers
Table 4-4 shows the CP15 system control registers you can access when CRn is c2.
4.2.4 c3 registers
Table 4-5 shows the CP15 system control registers you can access when CRn is c3.
Table 4-3 c1 register summary
Op1 CRm Op2 Name Type Reset Description
0c00SCTLRRW
-
a
System Control Register on page 4-25
1
ACTLR
b
RW 0x00000000 Auxiliary Control Register on page 4-27
2CPACRRW
-
c
Coprocessor Access Control Register on page 4-29
c1 0
SCR
de
RW 0x00000000 Secure Configuration Register
1
SDER
d
RW 0x00000000 Secure Debug Enable Register on page 4-31
2NSACR
RW
f
-
g
Non-secure Access Control Register on page 4-32
3
VCR
d
RW 0x00000000 Virtualization Control Register on page 4-34
a. Depends on input signals. See System Control Register on page 4-25.
b. RO in Non-secure state if NSACR[18]=0 and RW if NSACR[18]=1.
c. The reset value depends on the VFP and NEON configuration.
If VFP and NEON are implemented, and NEON is powered up, the reset value is
0x00000000
If VFP is implemented, and NEON is not implemented or powered down, the reset value is 0x80000000
If VFP and NEON are not implemented, the reset value is 0xC0000000 .
d. No access in Non-secure state.
e. SCR[6] is not implemented, RAZ/WI.
f. RW in Secure state and RO in the Non-secure state.
g.
0x00000000 if NEON present and 0x0000C000 if NEON not present.
Table 4-4 c2 register summary
Op1 CRm Op2 Name Type Reset Description
0 c0 0 TTBR0 RW -
1 TTBR1 RW - Translation Table Base Register 1
2 TTBCR RW
0x00000000
a
a. In Secure state only. You must program the Non-secure version with the required value.
Translation Table Base Control Register
Table 4-5 c3 register summary
Op1 CRm Op2 Name Type Reset Description
0 c0 0 DACR RW - Domain Access Control Register

ARM Cortex A9 Specifications

General

Architecture	ARMv7-A
Cores	1-4
SIMD Extensions	NEON
ISA	ARM
Microarchitecture	Cortex-A9
Instruction Width	32-bit
Data Width	32-bit
MMU	Yes
Instruction Set	ARMv7-A
Clock Speed	Up to 2 GHz
L1 Cache	32 KB Instruction, 32 KB Data (per core)
Process Technology	40 nm, 28 nm
Floating Point Unit	VFPv3
Pipeline Depth	8 stages
Power Consumption	Low power design