ARM Cortex A9 User Manual

System Control
ARM DDI 0388I Copyright © 2008-2012 ARM. All rights reserved. 4-31
ID073015 Non-Confidential
Access to coprocessors in the Non-secure state depends on the permissions set in the Non-secure
Access Control Register on page 4-32.
Attempts to read or write the CPACR access bits depend on the corresponding bit for each
coprocessor in Non-secure Access Control Register on page 4-32.
To access the CPACR, read or write the CP15 register with:
MRC p15, 0,<Rd>, c1, c0, 2; Read Coprocessor Access Control Register
MCR p15, 0,<Rd>, c1, c0, 2; Write Coprocessor Access Control Register
You must execute an ISB immediately after an update of the CPACR. See the ARM Architecture
Reference Manual for more information. You must not attempt to execute any instructions that
are affected by the change of access rights between the
ISB and the register update.
To determine if any particular coprocessor exists in the system, write the access bits for the
coprocessor of interest with b11. If the coprocessor does not exist in the system the access rights
remain set to b00.
Note
You must enable both coprocessor 10 and coprocessor 11 before accessing any NEON or VFP
system registers.
4.3.12 Secure Debug Enable Register
The SDER characteristics are:
Purpose Controls Cortex-A9 debug.
Usage constraints The SDER is:
• only accessible in privileged modes
• only accessible in Secure state, accesses in Non-secure state cause
an Undefined Instruction exception.
Configurations Available in all configurations.
Attributes See the register summary in Table 4-3 on page 4-6.
Figure 4-11 shows the SDER bit assignments.
Figure 4-11 SDER bit assignments
Reserved
31 10
2
SUNIDEN
SUIDEN

ARM Cortex A9 Specifications

General

Architecture	ARMv7-A
Cores	1-4
SIMD Extensions	NEON
ISA	ARM
Microarchitecture	Cortex-A9
Instruction Width	32-bit
Data Width	32-bit
MMU	Yes
Instruction Set	ARMv7-A
Clock Speed	Up to 2 GHz
L1 Cache	32 KB Instruction, 32 KB Data (per core)
Process Technology	40 nm, 28 nm
Floating Point Unit	VFPv3
Pipeline Depth	8 stages
Power Consumption	Low power design