ARM Cortex A9 User Manual

System Control
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• common to Secure and Non-secure states.
Configurations Available in all configurations.
Attributes See the register summary in Table 4-3 on page 4-6.
Figure 4-10 shows the CPACR bit assignments.
Figure 4-10 CPACR bit assignments
Table 4-37 shows the CPACR bit assignments.
31 24 23
22
21
20 19 0
cp11 cp10
ASEDIS
D32DIS
RAZ/WI RAZ/WI
30 29
Table 4-37 CPACR bit assignments
Bits Name Function
[31] ASEDIS Disable Advanced SIMD Extension functionality:
0 All Advanced SIMD and VFP instructions execute normally
1 All Advanced SIMD instructions that are not VFP instructions are UNDEFINED.
See the Cortex-A9 Floating-Point Unit Technical Reference Manual and Cortex-A9 NEON Media Processing
Engine Technical Reference Manual for more information.
If implemented with VFP only, this bit is RAO/WI.
If implemented without both VFP and NEON, this bit is UNK/SBZP.
[30] D32DIS Disable use of D16-D31 of the VFP register file:
0 All VFP instructions execute normally
1 All VFP instructions are
UNDEFINED if they access any of registers D16-D31.
See the Cortex-A9 Floating-Point Unit Technical Reference Manual and Cortex-A9 NEON Media Processing
Engine Technical Reference Manual for more information.
If implemented with VFP only, this bit is RAO/WI.
If implemented without both VFP and NEON, this bit is UNK/SBZP.
[29:24] - RAZ/WI.
[23:22] cp11 Defines access permissions for the coprocessor. Access denied is the reset condition and is the behavior for
non-existent coprocessors.
b00 Access denied. This is the reset value. Attempted access generates an Undefined Instruction
exception.
b01 Privileged mode access only.
b10 Reserved.
b11 Privileged and User mode access.
[21:20] cp10 Defines access permissions for the coprocessor. Access denied is the reset condition and is the behavior for
non-existent coprocessors.
b00 Access denied. This is the reset value. Attempted access generates an Undefined Instruction
exception.
b01 Privileged mode access only.
b10 Reserved.
b11 Privileged and User mode access.
[19:0] - RAZ/WI.

ARM Cortex A9 Specifications

General

Architecture	ARMv7-A
Cores	1-4
SIMD Extensions	NEON
ISA	ARM
Microarchitecture	Cortex-A9
Instruction Width	32-bit
Data Width	32-bit
MMU	Yes
Instruction Set	ARMv7-A
Clock Speed	Up to 2 GHz
L1 Cache	32 KB Instruction, 32 KB Data (per core)
Process Technology	40 nm, 28 nm
Floating Point Unit	VFPv3
Pipeline Depth	8 stages
Power Consumption	Low power design