ARM Cortex A9 User Manual

System Control
ARM DDI 0388I Copyright © 2008-2012 ARM. All rights reserved. 4-29
ID073015 Non-Confidential
To access the ACTLR you must use a read modify write technique. To access the ACTLR, read
or write the CP15 register with:
MRC p15, 0,<Rd>, c1, c0, 1; Read ACTLR
MCR p15, 0,<Rd>, c1, c0, 1; Write ACTLR
Attempts to write to this register in secure privileged mode when CP15SDISABLE is HIGH
result in an Undefined Instruction exception.
4.3.11 Coprocessor Access Control Register
The CPACR characteristics are:
Purpose • sets access rights for the coprocessors CP11 and CP10
• enables software to determine if any particular coprocessor exists in
the system.
Note
This register has no effect on access to CP14 or CP15.
Usage constraints The CPACR is:
• only accessible in privileged modes
[7] EXCL Exclusive cache bit.
The exclusive cache configuration does not permit data to reside in L1 and L2 at the same time. The
exclusive cache configuration provides support for only caching data on an eviction from L1 when the
inner cache attributes are Write-Back, Cacheable and allocated in L1. Ensure that your cache
controller is also configured for exclusive caching.
0 Disabled. This is the reset value.
1 Enabled.
[6] SMP Signals if the Cortex-A9 processor is taking part in coherency or not.
In uniprocessor configurations, if this bit is set, then Inner Cacheable Shared is treated as Cacheable.
The reset value is zero.
[5:4] - RAZ/WI.
[3] Write full line
of zeros mode
Enable write full line of zeros mode
a
. The reset value is zero.
[2] L1 prefetch
enable
Dside prefetch.
0 Disabled. This is the reset value.
1 Enabled.
[1] L2 prefetch
enable
Prefetch hint enable
a
. The reset value is zero.
[0] FW Cache and TLB maintenance broadcast:
0 Disabled. This is the reset value.
1 Enabled.
RAZ/WI if only one Cortex-A9 processor is present.
a. This feature must be enabled only when the slaves connected on the Cortex-A9 AXI master port support it. The L2-310 Cache Controller
supports this feature. See Optimized accesses to the L2 memory interface on page 8-7.
Table 4-36 ACTLR bit assignments (continued)
Bits Name Function

ARM Cortex A9 Specifications

General

Architecture	ARMv7-A
Cores	1-4
SIMD Extensions	NEON
ISA	ARM
Microarchitecture	Cortex-A9
Instruction Width	32-bit
Data Width	32-bit
MMU	Yes
Instruction Set	ARMv7-A
Clock Speed	Up to 2 GHz
L1 Cache	32 KB Instruction, 32 KB Data (per core)
Process Technology	40 nm, 28 nm
Floating Point Unit	VFPv3
Pipeline Depth	8 stages
Power Consumption	Low power design