ARM Cortex A9 User Manual

System Control
ARM DDI 0388I Copyright © 2008-2012 ARM. All rights reserved. 4-28
ID073015 Non-Confidential
• RW in Non-secure state if NSACR.NS_SMP = 1. In this case all bits
are Write Ignore except for the SMP bit.
Configurations Available in all configurations.
• In all configurations when the SMP bit = 0, Inner Cacheable
Shareable attributes are treated as Non-cacheable.
• In multiprocessor configurations when the SMP bit is set:
— broadcasting cache and TLB maintenance operations is
permitted if the FW bit is set
— receiving cache and TLB maintenance operations broadcast
by other Cortex-A9 processors in the same coherent cluster is
permitted if the FW bit is set
— the Cortex-A9 processor can send and receive coherent
requests for Shared Inner Write-back Write-Allocate accesses
from other Cortex-A9 processors in the same coherent cluster.
Attributes See the register summary in Table 4-3 on page 4-6.
Figure 4-9 shows the ACTLR bit assignments.
Figure 4-9 ACTLR bit assignments
Table 4-36 shows the ACTLR bit assignments.
UNP/SBZP
31 43210
65
L1 Prefetch enable
FW
SMP
7
EXCL
8
RAZ/WI
9
Parity_on
10
Alloc in one way
Write full line of zeros mode
L2 Prefetch hint enable
Table 4-36 ACTLR bit assignments
Bits Name Function
[31:10] - UNP or SBZP.
[9] Parity on Support for parity checking, if implemented:
0 Disabled. This is the reset value.
1 Enabled.
If parity checking is not implemented this bit reads as zero and writes are ignored.
[8] Alloc in one
way
Enable allocation in one cache way only. For use with memory copy operations to reduce cache
pollution. The reset value is zero.

ARM Cortex A9 Specifications

General

Architecture	ARMv7-A
Cores	1-4
SIMD Extensions	NEON
ISA	ARM
Microarchitecture	Cortex-A9
Instruction Width	32-bit
Data Width	32-bit
MMU	Yes
Instruction Set	ARMv7-A
Clock Speed	Up to 2 GHz
L1 Cache	32 KB Instruction, 32 KB Data (per core)
Process Technology	40 nm, 28 nm
Floating Point Unit	VFPv3
Pipeline Depth	8 stages
Power Consumption	Low power design