ARM Cortex A9 User Manual

System Control
ARM DDI 0388I Copyright © 2008-2012 ARM. All rights reserved. 4-7
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4.2.5 c4 registers
No CP15 system control registers are accessed with CRn set to c4.
4.2.6 c5 registers
Table 4-6 shows the CP15 system control registers you can access when CRn is c5.
4.2.7 c6 registers
Table 4-7 shows the CP15 system control registers you can access when CRn is c6.
Table 4-6 c5 register summary
Op1 CRm Op2 Name Type Reset Description
0 c0 0 DFSR RW - Data Fault Status Register
1 IFSR RW - Instruction Fault Status Register
c1 0 ADFSR - - Auxiliary Data Fault Status Register
1 AIFSR - - Auxiliary Instruction Fault Status Register
Table 4-7 c6 register summary
Op1 CRm Op2 Name Type Reset Description
0 c0 0 DFAR RW - Data Fault Address Register
2 IFAR RW - Instruction Fault Address Register

ARM Cortex A9 Specifications

General

Architecture	ARMv7-A
Cores	1-4
SIMD Extensions	NEON
ISA	ARM
Microarchitecture	Cortex-A9
Instruction Width	32-bit
Data Width	32-bit
MMU	Yes
Instruction Set	ARMv7-A
Clock Speed	Up to 2 GHz
L1 Cache	32 KB Instruction, 32 KB Data (per core)
Process Technology	40 nm, 28 nm
Floating Point Unit	VFPv3
Pipeline Depth	8 stages
Power Consumption	Low power design