ARM Cortex A9 User Manual

System Control
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4.2.8 c7 registers
Table 4-8 shows the CP15 system control registers you can access when CRn is c7.
Table 4-8 c7 register summary
Op1 CRm Op2 Name Type Reset Description
0 c0 0-3 Reserved WO - -
4
NOP
a
a. This operation is performed by the WFI instruction. See Deprecated registers on page 4-2.
WO - -
c1 0 ICIALLUIS WO - Cache operations registers
6BPIALLISWO-
7Reserved WO-
c4 0 PAR RW
- -
c5 0 ICIALLU WO - Cache operations registers
1ICIMVAUWO
-
2-3 Reserved WO -
4 ISB WO User Deprecated registers on page 4-2
6BPIALL WO
- Cache operations registers
c6 1 DCIMVAC WO
-
2DCISW WO -
0 c8 0-7 V2PCWPR WO - VA to PA operations
c10 1 DCCVAC WO - Cache operations registers
2 DCCSW WO -
4 DSB WO User Deprecated registers on page 4-2
5 DMB WO User
c11 1 DCCVAU WO - Cache operations registers
c14 1 DCCIMVAC WO -
2 DCCISW WO -

ARM Cortex A9 Specifications

General

Architecture	ARMv7-A
Cores	1-4
SIMD Extensions	NEON
ISA	ARM
Microarchitecture	Cortex-A9
Instruction Width	32-bit
Data Width	32-bit
MMU	Yes
Instruction Set	ARMv7-A
Clock Speed	Up to 2 GHz
L1 Cache	32 KB Instruction, 32 KB Data (per core)
Process Technology	40 nm, 28 nm
Floating Point Unit	VFPv3
Pipeline Depth	8 stages
Power Consumption	Low power design