ARM Cortex A9 User Manual

System Control
ARM DDI 0388I Copyright © 2008-2012 ARM. All rights reserved. 4-9
ID073015 Non-Confidential
4.2.9 c8 registers
Table 4-9 shows the CP15 system control registers you can access when CRn is c8.
See Invalidate TLB Entries on ASID Match on page 4-45.
4.2.10 c9 registers
Table 4-10 shows the CP15 system control registers you can access when CRn is c9.
See Chapter 11 Performance Monitoring Unit.
Table 4-9 c8 register summary
Op1 CRm Op2 Name Type Reset Description
0c3 0
TLBIALLIS
a
a. Has no effect on entries that are locked down.
WO - -
1
TLBIMVAIS
b
b. Invalidates the locked entry when it matches.
WO - -
2
TLBIASIDIS
b
WO - -
3
TLBIMVAAIS
a
WO - -
c5, c6, or c7 0
TLBIALL
a
WO - -
1
TLBIMVA
b
WO - -
2
TLBIASID
b
WO - -
3
TLBIMVAA
a
WO - -
Table 4-10 c9 register summary
Op1 CRm Op2 Name Type Reset Description
0c120PMCR RW
0x41093000 Performance Monitor Control Register
1PMCNTENSETRW
0x00000000 Count Enable Set Register
2PMCNTENCLRRW
0x00000000 Count Enable Clear Register
3 PMOVSR RW - Overflow Flag Status Register
4 PMSWINC WO - Software Increment Register
5 PMSELR RW
0x00000000 Event Counter Selection Register
c13 0 PMCCNTR RW - Cycle Count Register
1 PMXEVTYPER RW - Event Type Selection Register
2 PMXEVCNTR RW - Event Count Registers
c14 0 PMUSERENR
RW
a
0x00000000 User Enable Register
1PMINTENSETRW
0x00000000 Interrupt Enable Set Register
2PMINTENCLRRW
0x00000000 Interrupt Enable Clear Register
a. RO in User mode.

ARM Cortex A9 Specifications

General

Architecture	ARMv7-A
Cores	1-4
SIMD Extensions	NEON
ISA	ARM
Microarchitecture	Cortex-A9
Instruction Width	32-bit
Data Width	32-bit
MMU	Yes
Instruction Set	ARMv7-A
Clock Speed	Up to 2 GHz
L1 Cache	32 KB Instruction, 32 KB Data (per core)
Process Technology	40 nm, 28 nm
Floating Point Unit	VFPv3
Pipeline Depth	8 stages
Power Consumption	Low power design