ARM Cortex A9 User Manual

System Control
ARM DDI 0388I Copyright © 2008-2012 ARM. All rights reserved. 4-10
ID073015 Non-Confidential
4.2.11 c10 registers
Table 4-11 shows the CP15 system control registers you can access when CRn is c10.
4.2.12 c11 registers
Table 4-12 shows the CP15 system control registers you can access where CRn is c11.
4.2.13 c12 registers
Table 4-13 shows the CP15 system control registers you can access when CRn is c12.
Table 4-11 c10 register summary
Op1 CRm Op2 Name Type Reset Description
0c00
TLB Lockdown Register
a
RW 0x00000000 TLB Lockdown Register on page 4-35
c2 0
PRRR
b
RW 0x00098AA4 Primary Region Remap Register
1
NMRR
c
RW 0x44E048E0 Normal Memory Remap Register
a. No access in Non-secure state if NSCAR.TL=0 and RW if NSACR.TL=1.
b. PRRR[13:12] is not implemented, RAZ/WI.
c. NMRR[29:28] and NMRR[13:12] are not implemented, RAZ/WI
Table 4-12 c11 register summary
Op1 CRm Op2 Name Type Reset Description
0c00PLEIDR
RO
a
- PLE ID Register on page 4-36
2PLEASR
RO
a
- PLE Activity Status Register on page 4-36
4 PLEFSR
RO
a
- PLE FIFO Status Register on page 4-37
c1 0 PLEUAR Privileged R/W
User RO
- Preload Engine User Accessibility Register on page 4-38
1 PLEPCR Privileged R/W
User RO
- Preload Engine Parameters Control Register on page 4-39
a. RAZ if the PLE is not present.
Table 4-13 c12 register summary
Op1 CRm Op2 Name Type Reset Description
0 c0 0 VBAR RW
0x00000000
a
Vector Base Address Register
1 MVBAR RW - Monitor Vector Base Address Register
c1 0 ISR RO
0x00000000 Interrupt Status Register
1 Virtualization Interrupt Register RW
0x00000000 Virtualization Interrupt Register on page 4-40
a. Only the secure version is reset to 0. The Non-secure version must be programmed by software.

ARM Cortex A9 Specifications

General

Architecture	ARMv7-A
Cores	1-4
SIMD Extensions	NEON
ISA	ARM
Microarchitecture	Cortex-A9
Instruction Width	32-bit
Data Width	32-bit
MMU	Yes
Instruction Set	ARMv7-A
Clock Speed	Up to 2 GHz
L1 Cache	32 KB Instruction, 32 KB Data (per core)
Process Technology	40 nm, 28 nm
Floating Point Unit	VFPv3
Pipeline Depth	8 stages
Power Consumption	Low power design