ARM Cortex A9 User Manual

System Control
ARM DDI 0388I Copyright © 2008-2012 ARM. All rights reserved. 4-39
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4.3.20 Preload Engine Parameters Control Register
The PLEPCR characteristics are:
Purpose Contains PLE control parameters, available only in Privilege modes, to
limit the issuing rate and transfer size of the PLE.
Usage constraints The PLEPCR is:
• read/write register
• only accessible in privileged mode
• common to Secure and Non-secure states
• NSACR.PLE controls Non-secure accesses.
Configurations Only available in configurations where the Preload Engine is present,
otherwise an Undefined Instruction exception is taken.
Attributes See Table 4-12 on page 4-10.
Figure 4-19 shows the PLEPCR bit assignments.
Figure 4-19 PLEPCR bit assignments
Table 4-46 shows the PLEPCR bit assignments.
To access the PLEPCR, read or write the CP15 register with:
31 0
PLE wait statesRAZ
30 29 16 15 8 7
Block size mask Block number mask
Table 4-46 PLEPCR bit assignments
Bits Name Function
[31:30] - RAZ.
[29:16] Block size mask Permits Privilege modes to limit the maximum block size for PLE transfers.
The transferred block size is:
(Block size) & (Block size mask).
For example, a block size mask of 14’b11111111111111 authorizes the transfer of block sizes with
the maximum value of 16k * 4 bytes. A block size mask of 14’b00000000000000 limits block sizes
to 1 * 4 bytes.
[15:8] Block number mask Permits Privilege modes to limit the maximum number of blocks for a single PLE transfer.
The transferred block number is:
(Block number) & (Block number mask).
For example, a block number mask of 8’b11111111 authorizes the transfer of a maximum possible
number of 256 blocks. A block number mask of 8’b00000000 limits the transfer to only one block
of data.
[7:0] PLE wait states Permit Privilege modes to limit the issuing rate of PLD requests performed by the PLE engine to
prevent saturation of the external memory bandwidth.
PLE wait states specifies the number of cycles inserted between two PLD requests performed by the
PLE engine.
When PLE wait states is 8’b11111111, the PLE engine can issue one PLD request, a cache line, every
256 cycles.
When PLE wait states is 8’b000000000, the PLE engine can issue one PLD request every cycle.

ARM Cortex A9 Specifications

General

Architecture	ARMv7-A
Cores	1-4
SIMD Extensions	NEON
ISA	ARM
Microarchitecture	Cortex-A9
Instruction Width	32-bit
Data Width	32-bit
MMU	Yes
Instruction Set	ARMv7-A
Clock Speed	Up to 2 GHz
L1 Cache	32 KB Instruction, 32 KB Data (per core)
Process Technology	40 nm, 28 nm
Floating Point Unit	VFPv3
Pipeline Depth	8 stages
Power Consumption	Low power design