ARM Cortex A9 User Manual

System Control
ARM DDI 0388I Copyright © 2008-2012 ARM. All rights reserved. 4-38
ID073015 Non-Confidential
Table 4-44 shows the PLEFSR bit assignments.
Use the PLESFR to check that an entry is available before programming a new PLE channel.
To access the PLESFR, read the CP15 register with:
MRC p15, 0, <Rt>, c11, c0, 4; Read the PLESFR
4.3.19 Preload Engine User Accessibility Register
The PLEUAR characteristics are:
Purpose Controls whether PLE operations are available in User mode.
Usage constraints The PLEUAR is:
• common to Secure and Non-secure states
• accessible in User and privileged modes, regardless of any
configuration bit.
Configurations Only available in configurations where the Preload Engine is present,
otherwise an Undefined Instruction exception is taken.
Attributes See Table 4-12 on page 4-10.
Figure 4-18 shows the PLEUAR bit assignments.
Figure 4-18 PLEUAR bit assignments
Table 4-45 shows the PLEUAR bit assignments.
To access the PLEUAR, read or write the CP15 register with:
MCR p15, 0, <Rt>, c11, c1, 0; Read PLEAUR
MRC p15, 0, <Rt>, c11, c1, 0; Write PLEAUR
Table 4-44 PLESFR bit assignments
Bits Name Function
[31:5] - Reserved, RAZ/WI.
[4:0] Available entries Number of available entries in the PLE FIFO.
This is the difference between the total number of entries in the FIFO, that is configuration-specific, and
the number of entries already programmed.
31 10
U
RAZ
Table 4-45 PLEUAR bit assignments
Bits Name Function
[31:1] - RAZ.
[0] U User accessibility:
1 User modes can access PLE registers and execute PLE operations.

ARM Cortex A9 Specifications

General

Architecture	ARMv7-A
Cores	1-4
SIMD Extensions	NEON
ISA	ARM
Microarchitecture	Cortex-A9
Instruction Width	32-bit
Data Width	32-bit
MMU	Yes
Instruction Set	ARMv7-A
Clock Speed	Up to 2 GHz
L1 Cache	32 KB Instruction, 32 KB Data (per core)
Process Technology	40 nm, 28 nm
Floating Point Unit	VFPv3
Pipeline Depth	8 stages
Power Consumption	Low power design