ARM Cortex A9 User Manual

System Control
ARM DDI 0388I Copyright © 2008-2012 ARM. All rights reserved. 4-36
ID073015 Non-Confidential
4.3.16 PLE ID Register
The PLEIDR characteristics are:
Purpose Indicates whether the PLE is present or not and the size of its FIFO.
Usage constraints The PLEIDR is:
• common to Secure and Non-secure states
• accessible in User and privileged modes, regardless of any
configuration bit.
Configurations Available in all Cortex-A9 configurations regardless of whether a PLE is
present or not.
Attributes See Table 4-12 on page 4-10.
Figure 4-15 shows the PLEIDR bit assignments.
Figure 4-15 PLEIDR bit assignments
Table 4-42 shows the PLEIDR bit assignments.
To access the PLEIDR, read the CP15 register with:
MRC p15, 0, <Rt>, c11, c0, 0; Read PLEIDR
4.3.17 PLE Activity Status Register
The PLEASR characteristics are:
Purpose Indicates whether the PLE engine is active.
Usage constraints The PLEASR is:
• common to Secure and Non-secure states
• accessible in User and privileged modes, regardless of any
configuration bit.
Configurations Available in all Cortex-A9 configurations regardless of whether a PLE is
present or not.
1
31 20 16 15 1 0
FIFO
size
21
RAZ
RAZ
Table 4-42 PLEIDR bit assignments
Bits Name Function
[31:21] - -
[20:16] PLE FIFO size Permitted values are:
b00000 indicates the PLE is not present
b00100 indicates a PLE is present with a FIFO size of 4 entries
b01000 indicates a PLE is present with a FIFO size of 8 entries
b10000 indicates a PLE is present with a FIFO size of 16 entries.
[15:1] - RAZ.
[0] - A value of
1 indicates that the Preload Engine is present in the given configuration.

ARM Cortex A9 Specifications

General

Architecture	ARMv7-A
Cores	1-4
SIMD Extensions	NEON
ISA	ARM
Microarchitecture	Cortex-A9
Instruction Width	32-bit
Data Width	32-bit
MMU	Yes
Instruction Set	ARMv7-A
Clock Speed	Up to 2 GHz
L1 Cache	32 KB Instruction, 32 KB Data (per core)
Process Technology	40 nm, 28 nm
Floating Point Unit	VFPv3
Pipeline Depth	8 stages
Power Consumption	Low power design