ARM Cortex A9 User Manual

System Control
ARM DDI 0388I Copyright © 2008-2012 ARM. All rights reserved. 4-13
ID073015 Non-Confidential
4.2.18 Virtual memory control registers
Table 4-17 shows the Virtual memory control registers.
4.2.19 Fault handling registers
Table 4-18 shows the Fault handling registers.
4.2.20 Other system control registers
Table 4-19 on page 4-14 shows the other system control registers.
Table 4-17 Virtual memory registers
CRn Op1 CRm Op2 Name Type Reset Description
c1 0 c0 0 SCTLR RW
-
a
System Control Register on page 4-25
c2 0 c0 0 TTBR0 RW -
1 TTBR1 RW - Translation Table Base Register 1
2 TTBCR RW
0x00000000
b
Translation Table Base Control Register
c3 0 c0 0 DACR RW - Domain Access Control Register
c10 0 c2 0
PRRR
c
RW 0x00098AA4 Primary Region Remap Register
1
NMRR
d
RW 0x44E048E0 Normal Memory Remap Register
c13 0 c0 1 CONTEXTIDR RW - Context ID Register
a. Depends on input signals. See System Control Register on page 4-25.
b. In Secure state only. You must program the Non-secure version with the required value.
c. PRRR[13:12] is not implemented, RAZ/WI.
d. NMRR[29:28] and NMRR[13:12] are not implemented, RAZ/WI
Table 4-18 Fault handling registers
CRn Op1 CRm Op2 Name Type Reset Description
c5 0 c0 0 DFSR RW - Data Fault Status Register
1 IFSR RW - Instruction Fault Status Register
c1 0 ADFSR - - Auxiliary Data Fault Status Register
1 AIFSR - - Auxiliary Instruction Fault Status Register
c6 0 c0 0 DFAR RW - Data Fault Address Register
2 IFAR RW - Instruction Fault Address Register

ARM Cortex A9 Specifications

General

Architecture	ARMv7-A
Cores	1-4
SIMD Extensions	NEON
ISA	ARM
Microarchitecture	Cortex-A9
Instruction Width	32-bit
Data Width	32-bit
MMU	Yes
Instruction Set	ARMv7-A
Clock Speed	Up to 2 GHz
L1 Cache	32 KB Instruction, 32 KB Data (per core)
Process Technology	40 nm, 28 nm
Floating Point Unit	VFPv3
Pipeline Depth	8 stages
Power Consumption	Low power design