ARM Cortex A9 User Manual

System Control
ARM DDI 0388I Copyright © 2008-2012 ARM. All rights reserved. 4-14
ID073015 Non-Confidential
4.2.21 Cache maintenance operations
Table 4-20 shows the 32-bit wide cache and branch predictor maintenance operations.
4.2.22 Address translation operations
Table 4-21 shows the address translation register and operations.
Table 4-19 Other system control registers
CRn Op1 CRm Op2 Name Type Reset Description
c1 0 c0 2 CPACR RW
-
a
Coprocessor Access Control Register on page 4-29
a. The reset value depends on the VFP and NEON configuration:
If VFP and NEON are implemented, and NEON is powered up, the reset value is
0x00000000
If VFP is implemented, and NEON is not implemented or powered down, the reset value is 0x80000000
If VFP and NEON are not implemented, the reset value is 0xC0000000 .
Table 4-20 Cache and branch predictor maintenance operations
CRn Op1 CRm Op2 Name Type Reset Description
c7 0 c1 0 ICIALLUIS WO - Cache operations registers
6BPIALLISWO-
c5 0 ICIALLU WO -
1ICIMVAUWO
-
6BPIALL WO -
c6 1 DCIMVAC WO -
2DCISW WO -
c10 1 DCCVAC WO -
2 DCCSW WO -
c11 1 DCCVAU WO -
c14 1 DCCIMVAC WO -
2 DCCISW WO -
Table 4-21 Address translation operations
CRn Op1 CRm Op2 Name Type Reset Description
c7 0 c4 0 PAR RW - -

ARM Cortex A9 Specifications

General

Architecture	ARMv7-A
Cores	1-4
SIMD Extensions	NEON
ISA	ARM
Microarchitecture	Cortex-A9
Instruction Width	32-bit
Data Width	32-bit
MMU	Yes
Instruction Set	ARMv7-A
Clock Speed	Up to 2 GHz
L1 Cache	32 KB Instruction, 32 KB Data (per core)
Process Technology	40 nm, 28 nm
Floating Point Unit	VFPv3
Pipeline Depth	8 stages
Power Consumption	Low power design