ARM Cortex A9 User Manual

Revisions
ARM DDI 0388I Copyright © 2008-2012 ARM. All rights reserved. C-6
ID073015 Non-Confidential
No differences between issue D and issue E.
Table C-5 Differences between issue D and issue F
Change Location
PL310 renamed L2C-310 Throughout the book
VFPv3 corrected to VFPv3 D-32 Media Processing Engine on page 1-2
Cortex-A9 FPU hardware description rewritten for clarity Floating-Point Unit on page 1-2
SCU description extended Cortex-A9 variants on page 1-4
Dynamic branch prediction description added Dynamic branch prediction on page 2-2
Final paragraph removed Energy efficiency features on page 2-10
WFI/WFE corrected to Standby Table 2-2 on page 2-10
Renamed and rewritten for clarity Standby modes on page 2-11
Dormant mode clamping information removed Dormant mode on page 2-12
IEM support renamed and rewritten Power domains on page 2-13
Repeated material removed About the programmers model on page 3-2
Debug register description corrected Table 4-2 on page 4-5
Main ID Register values for r2p1 and r2p2 added Table 4-2 on page 4-5
Debug register name corrected Table 4-2 on page 4-5
Descriptions clarified and footnote added. Table 4-30 on page 4-20
Purpose description extended Cache Size Identification Register on page 4-21
System Control Register value corrected, and footnotes amended Table 4-3 on page 4-6
Bit [17] function corrected Table 4-35 on page 4-25
Footnote d corrected Table 4-15 on page 4-11
Purpose description extended Power Control Register on page 4-41
Configurations description corrected Configuration Base Address Register on page 4-42
Chapter renamed Chapter 5 Jazelle DBX registers
6.1 application specific corrected to address space specific About the MMU on page 6-2
Unified Main TLB description clarified Memory Management Unit on page 6-2
Duplicate information about page sizes removed
ASID description corrected and extended, and cross-reference added
TLB match process duplicate information about page sizes removed TLB match process on page 6-4
Synchronous and asynchronous aborts incorrect cross-reference removed Synchronous and asynchronous aborts on page 6-8
Cache features cross-reference corrected Cache features on page 7-2
Implementation information removed
Return stack predictions ARM or Thumb state replaced by instruction state Return stack predictions on page 7-7

ARM Cortex A9 Specifications

General

Architecture	ARMv7-A
Cores	1-4
SIMD Extensions	NEON
ISA	ARM
Microarchitecture	Cortex-A9
Instruction Width	32-bit
Data Width	32-bit
MMU	Yes
Instruction Set	ARMv7-A
Clock Speed	Up to 2 GHz
L1 Cache	32 KB Instruction, 32 KB Data (per core)
Process Technology	40 nm, 28 nm
Floating Point Unit	VFPv3
Pipeline Depth	8 stages
Power Consumption	Low power design