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ARM Cortex A9 User Manual

ARM Cortex A9
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Functional Description
ARM DDI 0388I Copyright © 2008-2012 ARM. All rights reserved. 2-12
ID073015 Non-Confidential
The debug channel remains active throughout a
WFI
instruction.
Dormant mode
Dormant mode enables the Cortex-A9 processor to be powered down, while leaving the caches
powered up and maintaining their state.
The RAM blocks that must remain powered up during Dormant mode are:
all data RAMs associated with the cache
all tag RAMs associated with the cache
outer RAMs.
The RAM blocks that are to remain powered up must be implemented on a separate power
domain.
Before entering Dormant mode, the state of the Cortex-A9 processor, excluding the contents of
the RAMs that remain powered up in dormant mode, must be saved to external memory. These
state saving operations must ensure that the following occur:
All ARM registers, including CPSR and SPSR registers are saved.
All system registers are saved.
All debug-related state must be saved.
A Data Synchronization Barrier instruction is executed to ensure that all state saving has
completed.
The Cortex-A9 processor then communicates with the power controller, using the
STANDBYWFI, to indicate that it is ready to enter dormant mode by performing a
WFI
instruction. See Communication to the power management controller on page 2-13 for
more information.
Before removing the power, the reset signals to the Cortex-A9 processor must be asserted
by the external power control mechanism.
The external power controller triggers the transition from Dormant state to Run state. The
external power controller must assert reset to the Cortex-A9 processor until the power is
restored. After power is restored, the Cortex-A9 processor leaves reset and can determine that
the saved state must be restored.
Shutdown mode
Shutdown mode powers down the entire device, and all state, including cache, must be saved
externally by software. This state saving is performed with interrupts disabled, and finishes with
a Data Synchronization Barrier operation. The Cortex-A9 processor then communicates with a
power controller that the device is ready to be powered down in the same manner as when
entering Dormant Mode. The processor is returned to the run state by asserting reset.
Note
You must power up the processor before performing a reset.

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ARM Cortex A9 Specifications

General IconGeneral
ArchitectureARMv7-A
Cores1-4
SIMD ExtensionsNEON
ISAARM
MicroarchitectureCortex-A9
Instruction Width32-bit
Data Width32-bit
MMUYes
Instruction SetARMv7-A
Clock SpeedUp to 2 GHz
L1 Cache32 KB Instruction, 32 KB Data (per core)
Process Technology40 nm, 28 nm
Floating Point UnitVFPv3
Pipeline Depth8 stages
Power ConsumptionLow power design

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