ARM Cortex A9 User Manual

Functional Description
ARM DDI 0388I Copyright © 2008-2012 ARM. All rights reserved. 2-13
ID073015 Non-Confidential
Communication to the power management controller
Communication between the Cortex-A9 processor and the external power management
controller can be performed using the Standby signals, Cortex-A9 input clamp signals, and
DBGNOPWRDWN.
Standby signals
These signals control the external power management controller.
The STANDBYWFI signal indicates that the Cortex-A9 processor is ready to
enter Power Down mode. See WFE and WFI standby signals on page A-6.
Cortex-A9 input signals
The external power management controller uses NEONCLAMP and
CPURAMCLAMP to isolate Cortex-A9 power domains from one another
before they are turned off. These signals are only meaningful if the Cortex-A9
processor implements power domain clamps. See Power management signals on
page A-7.
DBGNOPWRDWN
DBGNOPWRDWN is connected to the system power controller and is
interpreted as a request to operate in emulate mode. In this mode, the Cortex-A9
processor and PTM are not actually powered down when requested by software
or hardware handshakes. See Miscellaneous debug interface signals on
page A-23.
2.4.3 Power domains
The Cortex-A9 uniprocessor contains optional placeholders between the Cortex-A9 logic and
RAM arrays, or between the Cortex-A9 logic and the NEON SIMD logic, when NEON is
present, so that these parts can be implemented in different voltage domains.
2.4.4 Cortex-A9 voltage domains
The Cortex-A9 processor can have the following power domains:
• Cortex-A9 processor logic cells
• Cortex-A9 processor data engines
• Cortex-A9 processor RAMs.
Figure 2-4 on page 2-14 shows the power domains.

ARM Cortex A9 Specifications

General

Architecture	ARMv7-A
Cores	1-4
SIMD Extensions	NEON
ISA	ARM
Microarchitecture	Cortex-A9
Instruction Width	32-bit
Data Width	32-bit
MMU	Yes
Instruction Set	ARMv7-A
Clock Speed	Up to 2 GHz
L1 Cache	32 KB Instruction, 32 KB Data (per core)
Process Technology	40 nm, 28 nm
Floating Point Unit	VFPv3
Pipeline Depth	8 stages
Power Consumption	Low power design